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34 DESIGN007 MAGAZINE I SEPTEMBER 2021 ing the above into account, for all the required onboard power supplies. And this all takes up valuable real estate—in some cases, up to 30% of the board surface area. One solution is to combine up to eight DC-to-DC converters in the same IC package. e resultant IC has one power input and outputs eight power rails. is approach reduces the overall PDN size by allow- ing the use of small 0201 capacitors combined with an integrated multi DC-to-DC converter. Taking this strategy further creates a new challenge. As we move toward complete sys- tems in a package (SiP) components with more functionality, even more power inputs are required. e SiP package itself may require up to 12 individual sources to power the increased functionality. en, each supply requires dis- crete filtering components. e trend in lower DC voltages also requires tighter voltage noise tolerances and higher currents. Market demands are forcing product designers to create PDNs with greater density, higher power efficiencies, and lower costs, making the process even more challenging. e target impedance approach to analyzing the PDN is the combination of the worst-case transient current and the voltage noise specifi- cation, which act together to set the maximum allowable AC impedance with assured perfor- mance. But, as current demands increase and voltage noise fluctuation tolerances reduce, we must lower the AC impedance even fur- ther with higher density capacitance. is shi requires the use of more expensive, tighter- tolerance parts, such as capacitors capable of surviving higher currents—creating more heat in a reduced space. In practice, accurately calculating the tran- sient currents and the precise requirements for the target impedance can be difficult. Since we typically do not know the transient noise cur- rent excitation very accurately, it is customary instead to design the PDN to meet the required AC impedance profile. Also, it seems that the current portion of the target impedance equa- tion varies from point-to-point, on the board, depending on a host of intricate relationships. One must always apply engineering judgment in translating the information available into the requirements for a cost-effective PDN design. With the continuous trend to smaller feature sizes and faster signal rise times, planar capaci- tor laminate or embedded capacitor materials (ECMs) are becoming a cost-effective solu- tion to further improve power integrity. is technology provides an effective approach for decoupling high-performance ICs whilst also reducing electromagnetic interference. Plane pair cavity resonances contribute to emissions. Smaller plane separation implies less area of equivalent magnetic current at the plane pair edge, or equivalently less local fring- ing field volume, and therefore lower emis- sions for a given field strength. Embedded capacitance technology com- prises a very thin dielectric layer (0.24 – 2.0 mil) that provides distributive decoupling capaci- tance and takes the place of conventional dis- crete decoupling capacitors over 1 GHz. ese ultra-thin laminates replace the conventional Table 1: Embedded capacitor materials available in the ICD Dielectric Materials Library.

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