Issue link: https://iconnect007.uberflip.com/i/1424540
seem to be a lot of classes on DFT. What would you recommend to designers? Horner: e simple answer is to get to know your friendly test engineer. ey don't bite. But if they can incorporate some basic design for test rules; that's a good start. Normally you find out if you can get 60% to 80% testability put into the card automatically. e other so- lution, and this is where some of those auto- mated tools become very popular, is to do pre- dictive coverage. If they say, "I'm using AOI to cover this part of the circuitry, I have flying probe covering this part of the circuitry, and I have X-ray covering this part of the circuitry and boundaries scan covering this circuitry," they may find the overall test strategy is 100%. It's a question of which test solution is going to cover which response. It's got to be where it's going to pick up the responsibility to cov- Johnson: Are these tools a bit like using a DRC checker aer the fact? Horner: No, they're more upfront. While the electrical engineer is laying out a schematic, even before they lay out a board, they can be putting DFT into the card and it's catching it before it goes out to a PCB layout. You can iden- tify key nets and net pins that you must have access to. So, when you have circuitry where you have RF, high-speed digital, or microwave, and you can't put in test points or control cir- cuits, at least on the peripheral circuitry, you can get access. You may have to only do more of a functional test on those high-speed areas that you can't pick up using traditional ICT fly- ing probe and even boundary skin. Andy Shaughnessy: Bert, what advice would you give designers regarding DFT? ere doesn't