Issue link: https://iconnect007.uberflip.com/i/1426508
32 DESIGN007 MAGAZINE I NOVEMBER 2021 have a difficult time getting the device back up if it needs rework. I have been tenting vias with either dry film or liquid photoimageable (LPI) solder mask for over 30 years. e basic reason is to seal the via hole for vacuum test fixtures and to pre- vent voids in the solder mask for silk-screening the component legend. Vias can be partially plugged with non-conductive paste but there is a chance of cracks from encapsulated gas during soldering. Or they can be filled with non-conductive or conductive materials. Proper thermal management is necessary to keep each component within safe temperature limits. e junction temperature should never exceed the limit indicated in the manufactur- er's datasheet (generally between 125–175°C for silicon-based devices). e heat generated by each component is transferred to the out- side through the package and the pins. e two main techniques used to improve PCB thermal management consist in the creation of large ground planes and in the insertion of thermal vias. ermal vias are used to transfer heat from one layer to another. Unfortunately, FR-4 does not offer high thermal transfer. Copper-filled thermal vias provide an effi- cient heat dissipation path directly incorpo- rated into PCBs with placement directly under a surface-mounted IC (the heat source). is allows direct surface mount bonding for maxi- mum heat transfer using surface mount copper material. Specialized materials such as Kupri- on's copper thermal via paste are capable of filling vias of at least 5 mm in diameter. When fused, the copper paste converts to solid cop- per without melting, which provides thermal conductivities in the range of approximately 110-180 W * m -1* K -1 (watts per meter-Kelvin) and up to 290 W * m -1* K -1 for microvias (up to 25 mil in diameter). Engineers have debated the merits of hollow vias vs. solid vias for RF performance. ere is a great temptation to believe that making the via solid will somehow reduce the equiv- alent inductance of the structure. However, once the skin-effect kicks-in, in the megahertz range, then the current tends to only flow in the perimeter of the barrel. Conductive epoxy-filled is the best practice for the vias to have a finished diameter between 8–18 mil. is allows the epoxy—conductive or non-conductive—to be pushed through the hole completely, but not to run out. e asso- ciated aspect ratio is best if the depth-to-diam- eter is less than 10:1. A plate-shut process provides greater reli- ability for microvias, as opposed to filling with non-conductive ink and then plating over. Fill- ing vias creates a solid core. is allows for a flat surface to be plated, and keeps the solder at the assembly level from leaking through and compromising the solder joint. is provides for the most reliable finished assembly. e following materials can be used to ensure vias are sealed when filled: 1. A special plugging resin (e.g., Taiyo THP- 100 DX1 thermally curable permanent hole-filling material) is suitable for plated through-hole and via-in-pad applications. 2. Copper: Classic copper via filling methods involve using pure copper to fill the hole. 3. Silver conductive epoxy resin: is is an alternative for filling vias but is expensive and copper works more effectively (e.g., DuPont CB100 or Tatsuto AE3030 screen- printed material). PCBs that have copper-filled vias will stand up to the conditions presented by high power, radio frequency, microwave, and LED appli- cations. e high-power integrated circuits that run these types of PCBs use currents that a copper-filled via can withstand, but not a plated through-hole. A complete view of the current distribution can be visualized using a 3D solver. Figures 2 and 3 present three views of the conduction current at 18 GHz on a microstrip, hollow via, and solid via using Flomerics Micro-Strips, a 3D TLM solver: a) perspective view; b) top view of strip and ground plane; and c) bottom