Issue link: https://iconnect007.uberflip.com/i/1441485
JANUARY 2022 I DESIGN007 MAGAZINE 71 doing 8- to 15-micron lines as a basis for almost the last 15 years. Although they use a BT core and BT prepreg, they never got very good yields once they got under 20 microns, until they switched to using the Ajinomoto build-up film. Today, all eight of the Asian manufacturers of high-density packages use the ABF material pri- marily because it's a very well-engineered resin system that's robust, but it goes down extremely flat. at planarity is required for high density of imaging and developing, as well as etching. So, 20 microns is considered about the best you can do if you use laminate and prepreg. Below that and you have to start going to these engineered liquids or films that the Japanese perfected ini- tially, and now other sources are available for them. at's true for the thin film. I started out with the industry in semicon- ductor and thin film, not PC boards, and the different types of liquid dielectrics are extremely flat, which is one reason why glass is becoming so popular as an interposer. Amla: is is true and exactly what I was talking about: If you want to go below 20 microns, you can't do it with woven glass-reinforced materi- als. In chip packaging, they're doing 8-micron lines and 6-micron dielectrics, and that's basi- cally only possible with films. But on the main- stream high-speed side that can't happen, due to the loss alone. We did some computations for some people and found that if you take a 20-micron line, the loss is well beyond any budget. Plus, why would you want to do that? ere's no space constraint. You're not trying to put these high-density boards in the place of backplanes. But, for now, 3- or 4 mil is the dielectric spacing that people are looking at for high-speed boards. On the mobile phone side, yes, people are already going to semi-additive processes and using 35-micron lines, still with 2-mil dielec- trics. But on chip packaging, it has to be films, and that's what they're using. ey are not happy with a lot of the properties, because they still have some issues with warpage and what have you, but that's the direction that they've gone in. Ritchey: Right. Let me chime in here and say that there is no incentive for us designing high- speed boards to have a trace narrower than 4 mils. In fact, it's all negative when you do that, and that says we don't need dielectric thinner than 4 mils. Holden: Now what they can't do when dealing with chip scale packages and half a millimeter pitch and under is use 2-mil lines or smaller to break out. But once they get outside and they've got the room, they've got to expand that trace up to 3 or 4 mils to complete the routing. So, maybe that's probably what they should be selling, but they're instead making 2-mil lines. Ritchey: I couldn't allow that because that means the impedance was going to change dra- matically inside the package. At the data rates that I work with, we must have 50-ohm trans- mission lines right up to the die, so changing trace width in the package is not an option. Lee Ritchey