Issue link: https://iconnect007.uberflip.com/i/1449048
62 DESIGN007 MAGAZINE I FEBRUARY 2022 added, along with yield and reliability con- cerns. is has driven printed circuit board designers to increasingly rely on complex HDI structures to accomplish their routing. Stacked and staggered microvias and multiple lamination cycles are oen required. ese, too, come with yield and reliability concerns, not to mention increased cost. e exciting news is that a handful of for- ward-thinking PCB fabricators have invested in semi-additive processing capabilities and now provide an option for those outside of the high-volume consumer electronics indus- try to take advantage of the benefits of routing with much smaller trace and space constraints. With any change, there is a learning curve to be expected and both fabricators and design- ers are navigating this now. Some embrace change and jump in with both feet. Others take a more cautious approach and wait to see how this develops. From a fabrication standpoint, at a sur- face level, these semi-additive processes are a simple addition to the processes that they are currently using day in and day out. ese pro- cesses move the constraint from the etching process to the photolithography process yet are still run with the existing laser direct-imag- ing equipment and all the same chemistries for electroless and electrolytic copper. Once the traces are formed, the circuit panel processes through fabrication in the same fashion as a subtractive etch layer would. As with any change to process, there is a learning curve and things that can catch you off guard. For example, again from the fabrica- tion perspective, there are certain resists that resolve these finer feature sizes better than others and some process tweaks that need to be done to the photolithography process for the best results. And, with these finer feature sizes, the handling and cleanliness become more important. Arguably, while this can seem to be a challenge, once resolved, yield and reli- ability increase for all product, not only the SAP layers. Switching perspective to the PCB designers' adoption of features created with SAP pro- cesses, there is a similar learning curve. All the major design tools are able to accommodate these features sizes, with relatively little addi- tional effort. At the same time, designers are working hard to understand the impacts. For some, simply reducing overall size, or reduc- ing layer count is the critical element. For oth- ers, signal integrity is key. ere is a continu- ally growing body of knowledge around this design space. When you decrease line width, there is an impact on impedance and the best way to mitigate this or to use it to the best advantage is very design dependent. ere will be many tech sessions through- out the next several months that drill down into these considerations, looking both at the impacts at the board level and at the impact to the overall electronics design. One inter- esting case quickly showed the improvement in power consumption once the design was reviewed more holistically rather than just from the bare board perspective. As much as things change, they stay the same. As this effort is going on, industry associations such as IPC are working to establish guide- lines for acceptance and reliability. Designers are requesting design guidelines, and as men- tioned in a previous column, I am not neces- sarily in favor of that until we understand more about how to be apply the new capability. is is our opportunity to think outside of the box and collaborate on how to best reset the tra- ditional technology curve. is is an exciting time for the PCB industry. Change is inevita- ble. Lean in and take advantage of these new capabilities. DESIGN007 Tara Dunn is the vice president of marketing and business development for Averatek. To read past columns or contact Dunn, click here.