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60 SMT007 MAGAZINE I APRIL 2022 ere is still work to do to see qualification of all machine communications against the IPC- CFX standard, but the number is increasing and accelerating with time. Other standards, such as the IPC Digital Twin, published at the end of 2020, are also poised to bring another level of interoperability throughout the indus- try, this time related to the secure exchange of data at a system level between previously diffi- cult-to-bridge silos. e Industry 4.0 gold rush is effectively over once interoperability is established. Smart Industry 4.0 manufacturing is now at a "Gold- ilocks moment." Rather than feeling the cost of data acquisition, operations are feeling the benefits from the use of such data. Value is created through the contextualization of col- lected information and relating operations together with production configurations, product design and BOM information, mate- rials and tooling data—the holistic analysis of which detects and measures variation, identi- fies potential defects, and triggers actions and alerts that improve throughput, on-time deliv- ery, quality, and productivity. For those who want to differentiate them- selves to gain competitive advantage, it can be done today with minimal cost and risk as com- pared to the gold rush days of Industry 4.0, if you are careful about the hardware and so- ware tools that you select; those IPC quali- fied solutions that provide IIoT-based, plug- and-play exchange of data. Today is when the really smart people invest in Industry 4.0. Is that you? SMT007 Michael Ford is the senior direc- tor of emerging industry strategy for Aegis Software. To read past columns or contact Ford, click here. For many years, a bottleneck in technological development has been how to get processors and memories to work faster together. Now, research- ers at Lund University in Sweden have presented a new solution integrating a memory cell with a pro- cessor, which enables much faster calculations, as they happen in the memory circuit itself. In an article in Nature Electronics, the researchers present a new configuration, in which a memory cell is integrated with a vertical transistor selector, all at the nanoscale. This brings improvements in scal- ability, speed and energy efficiency compared with current mass storage solutions. The fundamental issue is that anything requiring large amounts of data to be processed, such as AI and machine learning, requires speed and more capac- ity. For this to be successful, the memory and processor need to be as close to each other as possible. In addition, it must be possible to run the calculations in an energy-effi- cient manner, not least as current technology gen- erates high temperatures with high loads. The problem of processors' computations hap- pening much faster than the speed of the memory unit has been well known for many years. In tech- nical terms, this is known as the "von Neumann bottleneck." The bottleneck happens because the memory and computation units are separate, and it takes time to send information back and forth via what is known as a data bus, which limits speed. "Processors have developed a lot over many years. On the memory side, storage capacity has steadily increased, but things have been pretty quiet on the function side," says Saketh Ram Mamidala, doctoral student in nanoelectronics at Lund Uni- versity and one of the authors of the article. (Source: Lund University) Nanowire Transistor With Integrated Memory to Enable Future Supercomputers

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