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APRIL 2022 I DESIGN007 MAGAZINE 73 Electrically testing assembled circuit boards in a high-volume production environment requires a significant amount of engineer- ing resources to develop the fixtures and programming required for in-circuit testing. Increasingly, the more complex semiconduc- tor devices feature bus technology, enabling the potential to rapidly access thousands of test nodes for evaluating each component's function and interconnection integrity. Network access can be made from board edge contactors or by surface probe contact to a few designated semiconductor terminals. is is an extremely thorough test method, enabling both in-circuit test coverage and sys- tem diagnostics. Implementing boundary scan negates the need for the traditional ICT "one node per net" requirement (at least on the devices furnished with self-test capability). JTAG Test per IEEE 1149.1 Joint Test Action Group ( JTAG) is a team of test engineering specialists that developed a standard procedure for verifying designs and testing complex circuit board assemblies. Although the process requires that unique test programs be generated before use, the pro- gramming provides a cost-effective method for testing products having restricted surface area for probe interface. is boundary-scan test architecture offers the capability to effi- ciently test high-terminal-density core logic components, capturing functional data while the device(s) operate normally. Boundary- scan cells built into each device capture data from core logic signals. is captured data is then serially shied out and externally com- pared to projected results (Figure 1). Boundary scan testing can identify structural fault locations, even beneath array-configured semiconductor packaging, without requir- ing physical access to all nodes on the circuit board. In a typical boundary scan test, the tes- ter sends diagnostic signals to the device's data input pin. e boundary-scan cells capture the signals and serially shi them through the core logic. e output is then serially shied out of the core through the data output pin. Test Node Access Requirements e JTAG boundary scan test technique uses a shi register latch cell built into each exter- nal connection of every boundary scan com- patible device. One boundary scan cell is con- tained in the integrated circuit line adjacent to each I/O pin or terminal, and when used in the shi register mode it can transfer data along to the next cell in the device. ere are defined entry and exit points for the data to enter and exit the device, and it is therefore possible to progressively link several devices together. e test equipment typical of that developed by JTAG Technologies (Figure 2) offer maxi- mum flexibility and independence and can be Figure 1: Basic concept of boundary scan testing. (Source: Altera Corporation)

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