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28 DESIGN007 MAGAZINE I MAY 2022 monics) is multiples of 1 GHz, then noise can be injected into the plane cavity. When the clock or data harmonics overlap with the cav- ity resonant frequencies, there is the potential for long-range coupling between any signals that run through the cavity, thus affecting sig- nal integrity as a consequence of inadequate power integrity. Plane cavity resonance and emissions can be reduced as follows: 1. A thin dielectric, in the plane cavity, is the most effective way of reducing the peak amplitude of the modal resonance. It reduces spreading inductance and the impedance of the cavity, and also reduces the resonance peaks by damping the high-frequency components. 2. RC terminations, of 3R5 in series with 10nF connected across the plane pair and placed along the board edges, are generally sufficient to reduce the resonance peaks. 3. e parallel resonant frequencies, of the cavity, can be pushed up above the maximum bandwidth of the signals by reducing the plane size and by adding stitching vias between (similar) planes of a cavity. When a signal's EM energy propagates from the driver to the receiver along a transmission line, it changes along its length. e original signal will be received with varying degrees of distortion and degradation. is signal dis- tortion happens due to factors such as imped- ance mismatch, reflections, ringing, crosstalk, dielectric loss, jitter, and ground bounce. e PCB designer's primary objective should be to minimize these issues at the source, so that any signal distortion is eliminated. Key Points • Reflections can be caused by using a drive strength that is too high for the available load. • Over/undershoot can be attributed to overdriving the transmission line using a higher than required drive strength setting on the driver. Figure 6: Amplitude, at the far end of planes, as the input frequency is swept. (Source: Eric Bogatin)

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