Issue link: https://iconnect007.uberflip.com/i/1467185
24 DESIGN007 MAGAZINE I MAY 2022 drive strength than required or over-termina- tion on the receiver side by using an external resistor value that is higher than the character- istic impedance of the transmission line. e degradation of the signal due to overdriving the transmission line might be sufficient to result in system failure. On-Die Termination On-die terminations (ODT) can be used with some memory devices to match the transmis- sion line and dampen the reflections. Incorpo- rating a resistive termination within the DRAM device improves the signaling environment by reducing the electrical discontinuities intro- duced with off-die termination. DDR4 and DDR5 technology, like DDR3, include ODT on the data I/O pins. is feature is controlled by the ODT pin and consumes additional power when activated. e ODT and the output driver on DDR4 devices include additional mode register settings over the previous DRAM to increase system flexibility and optimize signal integrity. e ODT impedance can vary from 34-240 Ω in receive mode and 34-48 Ω in trans- mit mode in Figure 2. DDR4 signal-ended sig- nals are normally routed on 40 Ω transmission lines so, for short trace lengths with one load, a 40 Ω ODT is perfect. However, since the ODT and driver strength are soware selectable, one can validate and tune the strength during the testing phase of development. Series Termination Unfortunately, drivers do not have the same impedance as the transmission line (typically 10–35 Ω) so series terminations are used to balance the impedance, match the line, and minimize reflections, particularly on long traces where ODT is not provided. Imped- ance matching slows down the rise and fall times, reduces the ringing (over/undershoot) of signal drivers, and enhances the quality of a high-speed signal. e ringing is dramatically reduced by adding a series terminator as in Figure 3. From this, we can see that the imped- ance has to be matched—but to what value? In Figure 4, using a 12 mA LVCMOS 1.8V Figure 2: Micron 4 Gb DDR4-3200 SDRAM with ODT. (Source: iCD termination Planner)