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JULY 2022 I DESIGN007 MAGAZINE 55 e speed, accuracy, and ease of setup of EM simulators for PCB designs make it less acceptable to blindly leverage data sheets and past designs. Engineers need to add EM sim- ulation to their checklist when verifying per- formance for dynamic operation. Simple DC checks and lumped SPICE modeling without PCB parasitics are no longer enough with the density and speed of multi-gigabit electronics powered by ever decreasing power rail volt- ages. DESIGN007 Heidi Barnes is a senior appli- cation engineer for high-speed digital applications at Keysight Technologies. She holds five patents and is a winner of NASA's Silver Snoopy award. Figure 3: A simple stepped impedance Beatty test structure in the upper left is easy to understand with basic telegrapher equations for impedance reflections in the time domain shown in the graph on the bottom left. Traces to the board edge can help with verifying as-fabricated stack-up dimensions. In the bottom right is the frequency domain EM simulated S-parameter that is converted to the time domain for the TDR data.