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44 DESIGN007 MAGAZINE I OCTOBER 2022 interconnect. From this data, the designer can assign the associated land pattern geometries and the pad-stack pre-established in the CAD systems library. For those components with- out existing pad-stack data, the manufacturer's mechanical and electrical data must be col- lected to enable the creation of new parts in the systems library. While a significant number of semiconduc- tor packages will have a moderate level of com- plexity (I/O and terminal pitch), others may have an excessively high I/O density. When assessing the PCB design complexity, first con- sider the component area to board area ratio. For example, the "standard" level of complex- ity will represent what the individual fabrica- tors recommend for the highest yield and most favorable unit quality. When component den- sity and area reserved for interconnect exceed the space defined by the circuit board outline and established maximum layer count, design- ers will need to migrate to a higher level of fab- rication technology. e interconnect com- plexity may necessitate more circuit layers or an increase in interconnect density. Two fab- rication methods can be applied when the sur- face area for component interface is restricted: adding additional layers to the core or base structure (increasing overall board thickness) or adopting sequential build-up (SBU) PCB fabrication. Advances in Circuit Fabrication Capability Printed circuit board fabrication process capabilities have continued to expand on a global scale. Fabrication process capability from one supplier to another, however, is not likely to be equal. is is because of the con- tinuous advancement in related chemistries, processing systems, materials, and overall process control. Ensuring the success of the end-product functionality requires an under- standing of the selected fabricator's primary capability attributes and how greater design complexity will affect the PCB producibility and cost. To ensure a successful outcome for the HDI circuit board, it is important that the designer recognize the manufacturing process complexities and associated cost impact when implementing more advanced fabrication pro- cedures. While a majority of the components will require a relatively moderate circuit intercon- nect density, the high I/O array-configured components will pose the most challenging aspect of the circuit routing process. Narrow conductors routed in parallel will generally have a conductor separation that is equal to the conductors' width. e s pacing s eparat- ing the circuit conductors must also consider the established minimum electrical clearance required for fabrication process variables, sol- der-mask adhesion, land pattern features, via land patterns, and other fixed elements on the board. One answer for solving conductor rout- ing roadblocks is to adopt blind via-in-land techniques to transfer a majority of the inter- connect responsibility to the circuit boards' sub-surface layers. Adapting blind and buried microvias and furnishing pre-defined routing channels will best facilitate efficient routing of these oen very fi ne-pitch and array te rminal configured s emiconductor p ackages. W hen establishing copper conductor width and spac- ing of the circuit, the IPC-2226, for example, defines three HDI complexity levels for both external and internal locations. A relatively few companies can produce Cu conductors as narrow as 25 μm (~0.001″) but they likely rely on using dielectric materials that have a very The interconnect complexity may necessitate more circuit layers or an increase in interconnect density.