Issue link: https://iconnect007.uberflip.com/i/1481368
OCTOBER 2022 I DESIGN007 MAGAZINE 59 issues in any of our major disciplines: signal integrity, power integrity, or electromagnetic compatibility. At locations and frequencies where the impedance is high, a signal via going through the power-ground plane cavity will introduce a dip in the trace's transfer function (S 21 ), which could be a signal-integrity prob- lem. At the same locations and frequencies, power noise will be higher and if at those fre- quencies there is sufficient excitation energy from our circuit, the conducted noise can create power integrity issues and the circuit potentially could also radiate enough to create electromagnetic compatibility issues. If we determine that the resonances could impose a risk to the operation of our circuit, we have a few options to deal with it. One pos- sibility is to push the resonance frequencies high enough that our high-speed signals or power noise from our circuit will not excite them. Since we oen use power planes to feed multiple electronic devices on our boards, this possible solution depends on how many devices we need to feed and what are our con- straints for their placement. If this mitigation does not work, we must find a way to suppress the modal resonances. One "easy" solution is if the density of our bypass capacitors becomes so high that eventually the cumulative imped- ance of bypass capacitors become dominant at the resonance frequencies. While this is a practical possibility and may oen happen in very dense and physically small applications, large boards may require too many components to make this a viable option. Another alternative is to use power- ground plane pairs on thin enough laminates that naturally will suppress modal resonances. As it was explained and documented 6 , the natural attenuation of a power-plane pair increases with decreasing dielectric thickness. With medium and large size boards, a dielec- tric thickness of 25 mm (1 mil) or less greatly suppresses the resonances. As an illustration, Figure 4 shows measured transfer impedance plots on the same board design manufactured with different dielectric thickness values. However, laminates thinner than 75 mm (3 mils) come with a price premium, and we also need to consider the usual stackup require- ments calling for symmetry. is means we cannot just use one thin laminate layer, we need to use them in pairs in the stackup, even if the circuit would otherwise require only one. Also, in case only a smaller portion of a larger board would require the suppression of plane resonances, we will end up with the same thin laminate horizontally everywhere on the board, also where you don't really need it. In those applications we can consider another potential solution: terminating the planes 7 , just as we reduce trace resonances by connect- Figure 4: Transfer impedance plots of measured transfer impedances with different laminate thickness values 6 .