Issue link: https://iconnect007.uberflip.com/i/1489778
JANUARY 2023 I DESIGN007 MAGAZINE 17 In next-generation devices that are being fabricated in process nodes of single digit nm channel lengths, we are seeing rise times/fall times of 0.1 ns (100 ps) or faster. is gives us TELs of about 0.6 inch and critical lengths of 0.3 inch or shorter. From this we can see that we can no lon- ger expect to be able to route our FPGA traces outside the perimeter of the FPGA body before adding our series termination resistors for successful signal integrity per- formance. To successfully solve this problem, the board designer will need to employ formed embedded resistors to the PCB structure. is technique uses a specialty layer of the PCB structure that has two different con- ductive materials on the same layer. One is the traditional copper, while the other is a resistive material such as nickel-phosphorous (Ni-P) that is used to create the resistors in line with the pins/vias of the FPGA/BGA ball. Now, to the question of process node: Process node refers to the length of the channel formed between the drain and source of a MOSFET by the gate of the MOSFET. Figure 12 shows an example of a traditional MOSFET struc- ture. As the length of the channel gets shorter, the time it takes an electron to move from the drain to the source gets shorter (faster). is, in turn, is what leads to the faster and faster rise times/fall times in modern devices. is is also why we say that rise time/fall time and not clock frequency is the determining factor for when signal integrity rules must be applied to a design. But that is a discussion for a future article. Regarding the issue of how to escape route out of modern FPGAs: Aer we incorporate the embedded resistor for the series termina- tion we need for signal integrity, we still have the issue of crosstalk for the parallel traces on adjacent layers. e main technique to use is trace separation in the Z-axis. In the event that you are not able to get a suf- ficient amount of separation/offset between the traces on the adjacent layers, it will be nec- essary to add additional plane layers to provide shielding/isolation between the trace layers. is approach has its own problems due to the need to add many layers to the board, which increases both mass and overall manufacturing complexity from the increased layer count, as well as the signal integrity desire to always add planes as pairs for Vcc/RTN both for planar capacitance for signal integrity and for proper Z-axis copper balancing for manufacturability. is too is a discussion for a future article. As we have seen, with the reduction in package size and increase in device speeds, escape routing FPGAs/BGAs continues to pose significant challenges to the modern PCB designer. DESIGN007 References 1. "Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs," PhD thesis by Xingsh- eng Wang at University of Glasgow, May 2010. Kris Moyer, CID/CID+, is an IPC design instructor and chair of the IPC 1-13 committee. Figure 12: Schematic view of a surface channel MOSFET device indicating physical gate length, channel width, and physical gate dielectric oxide thickness (t ox) 1 .