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20 DESIGN007 MAGAZINE I JANUARY 2023 1024 bits/s) is used to stimulate IBIS models in a transmission line configuration and, at the receiver, results in an eye diagramthat visual- izes the signal quality. To get a quantitative view of signal integrity performance, other measurements can be applied to the eye-dia- gram pattern, including eye height, eye width, signal amplitude, comparative delay, slew rate and setup/hold times. e measured values can then be compared with the JEDEC speci- fication. e quality of a high-speed digital signal can be quickly determined by using a compliance mask overlay on the eye diagram display (Fig- ure 1). A typical mask includes both time and amplitude limits. e blue area is keep-out. e mask template can be configured based on the JEDEC specification, in which the mid- dle section of the mask is made up of the setup/ hold time and stable voltage threshold specifica- tions. Masks can also be customized to test cer- tain specifications. By applying a mask test to the eye diagram, one can quickly tell if the sig- nal can meet the overall signal integrity require- ment. Unfortunately, mask dimensions are oen difficult to determine from the specifications. Eye diagrams include voltage and time samples of the data acquired at some sample rate below the data rate. In Figure 2, the bit sequences (le) are superimposed over one another to obtain the final eye diagram (right). What an eye diagram (Figure 3) can tell us: • AC timing noise or jitter, which is indicated by horizontal thickness • AC noise or reflections, which is indicated by vertical thickness of the bunches • e unit interval or symbol duration, which is equivalent to the center-to-center spacing of the crossovers • e peak-to-peak voltage • Overshoot and undershoot above/below the peak-to-peak waveform • Whether the ring back is above or below the peak-to-peak waveform • Rise/fall time, which can be measured from 10% to 90% of the rising/falling edge • e comparative delay between two or more signals Jitter arises when a rising or falling edge occurs at times that differ from the ideal. Some edges occur early; some occur late. In a digi- tal circuit, all signals are transmitted with ref- erence to a clock signal. e deviation of the digital signals as a result of reflections, inter- Figure 2: Formation of an eye diagram.