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16 DESIGN007 MAGAZINE I JANUARY 2023 on the same signal layer, as well as traces on the adjacent signal layers of the dual strip- line. e parallelism on adjacent layers is the bigger problem for signal integrity, as this can lead to crosstalk if the critical length is exceeded. To understand this concern we must under- stand that critical length is half the transition electrical length (TEL). To understand this, we must understand that TEL is the distance the signal will travel on the transmission line (trace) during the time the signal is being actively driven. is is the rise time/fall time of the digital signal. To calculate the TEL we must determine the velocity of propagation on the transmission line, using the following equation. Equation 1 Where: D k = dielectric constant c = speed of light v = velocity of propagation Using a little algebraic manipulation, Equation 1 becomes: Equation 2 Now assuming a standard FR-4 with a Dk of 4.0 and using imperial units (inches), we get the following: c = 983.6 x 10 6 ft/s √Dk = √4 = 2 v = (983.6 x 10 6 ft/s) / 2 = 491.8 x 10 6 ft/s (491.8 x 10 6 ft/s) x (12 in/ft) = 5.901 x 10 9 in/s (5.901 x 10 9 in/s) x (1 x 10 -9 ns/s) = 5.901 in/ns From this we see that if our rise time/fall time is 1 ns, we have approximately 6 inches for our TEL, making the critical length of half TEL about 3 inches. From this we can see that we can very easily escape out of our FPGA without significant SI issues before we need to add our series termination resistors. Modern FPGAs such as the AMD Xilinx Virtex UltraSCALE+ FPGA in 16 nm process have switching speeds as fast as 0.250 ns (Fig- ure 11). From this, and by returning to Equa- tion 2 again, we get a TEL of 1.475" and a criti- cal length of 0.738". Figure 11: Modern FPGAs have switching speeds as fast as 0.250 ns.