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54 PCB007 MAGAZINE I JANUARY 2023 Feature Article by Charles E. Bauer, Ph.D. TECHLEAD CORPORATION When talking about chip packaging impacts on substrates and electronic manufacturing services (EMS) providers, the focus mostly lies on large packages and very high I/O, fine pitch components; rightly so in most cases. However, several current packaging trends offer a new path forward to simplification and, thereby, cost reduction in both the printed wiring board (PWB) and EMS supply chains. A handful of key technologies support these advances. rough silicon vias (TSV), while tracing their origins back to the invention of the transistor and found in a few supercomput- ers during the 1980s, really came onto the vol- ume manufacturing scene between 2005 and 2010. Since that time, rapid advances in pro- cess control and yield led to very high-density memory implementations. TSV now proves a key enabler in the evolution of chiplet archi- tectures. e second key technology development came in the form of silicon and glass substrate development. Silicon substrates entered the scene in a significant manner during the 1990s but, until recently, proved too expensive for all but the most esoteric applications. e avail- ability of old node fabrication equipment that flooded the market around 2008–10, opened the door to more reasonably priced Si sub- strate and provided an easy path to the current chiplet architecture, particularly for large IC OEMs. e advent of glass substrates, driven The Impact of Chip Packaging

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