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26 PCB007 MAGAZINE I JANUARY 2023 can reduce the number of build-up layers in the substrate by embedding active compo- nents and bridge die directly into the FOWLP structure, and by using through mold copper posts that allow direct vertical interconnection between different layers. ese structural fea- tures allow elimination of additional routing layers in the build-up substrate. Furthermore, FOWLP can be directly assembled to the PCB without the use of a build-up substrate (Figure 2c). In this pack- age, advanced high-density interconnect in the RDL build-up layers of the FOWLP can provide interconnection between the high- density chiplets to the low-density device PCB. Another advantage of this package configuration is the ability to commit only known good modules (KGMs), of the high- density chiplets to the fan-out package in the build-up process. FOWLP can provide a sim- pler vertical package build-up structure with less interfacial stress and a lower package cost, resulting in better overall package reliability. Deca Technologies' M-Series is a key tech- nology that enables FOWLP to act as an organic high-density interposer to provide lateral and vertical interconnect between chiplets without the use of a silicon interposer or a build-up substrate. M-Series Gen 1 RDL build-up has 10 µm L/S and can accommodate 50 µm bond pad pitch. M-Series Gen 2 scales down to 2 µm L/S with 20 µm bond pad pitch. Deca's roadmap will drive down the intercon- nect scaling to 1.5 µm L/S and beyond for the succeeding M-Series generations. M-Series Gen 2 will enable a high-density fan-out tech- nology solution for many applications. Figure 3 makes a comparison of M-Series Gen1 with silicon bridge technology and shows how future M-Series Direct (MDx) with 1.5 µm L/S can further improve the circuit density and performance. Skywater is currently working with Deca Technologies to bring M-Series Gen 2 and future technologies to our advanced packaging facility in Kissimmee, Florida, to drive the next generation of advanced packaging onshore. FOWLP technology eliminates the use of a Si interposer and build-up substrate, simplifying the structure of future 3D solutions. e benefits of FOWLP make it a promis- ing technology for the future of microelectron- ics. As this technology continues to evolve, we can expect to see more powerful and efficient devices that offer improved performance and functionality at a lower cost. PCB007 Charles Woychik is senior direc- tor of advanced packaging plat- forms at SkyWater Technology Foundry. Figure 3: Comparison between heterogenous integration packages using a) an embedded silicon bridge die; b) M-Series Gen 2; and c) M-Series Direct (MDx).