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58 DESIGN007 MAGAZINE I FEBRUARY 2023 in favor of more environmentally friendly and less costly methods. at aside, with ongoing advances in semi- conductor technology design, packaging and interconnection innovations, and improved manufacturing technologies, the feature size of integrated circuits has continually decreased. Correspondingly, the operating speed of inte- grated circuits has increased with each new generation. Many in the electronics indus- try hope and expect that this trend will con- tinue into the foreseeable future, though most acknowledge that there are limits to the mate- rials and physics of semiconductor technology. One thing that is well known and understood is that for the highest operating speed, it is desirable to have short interconnection paths between electronic elements, both on an indi- vidual integrated circuit and between the ter- minals of interconnected chips, whether in an MCM, SiP, or discrete package. e challenge of design is that there are oen conflicting requirements. What is an advan- tage to one area of production can be a detri- ment to another, or even negatively impact the performance of the design itself. One such example is pad pitch. As termination pitches continue to shrink, from an assembler's per- spective it remains desirable to have a large pad pitch, for a larger pad pitch will improve yield and reduce the overall cost of assembly at the board level. Unfortunately, the large pads typically mean a larger package and a greater capacitive loading at the termination, thus a larger PCB and greater cost for the elements to be interconnected. Figure 1: An "ahead of the curve" 3D interconnection concept, the OTT concept proposed partitioning circuit design to create both a simpler PCB and more controllable high-speed interconnections between ICs. In 2005, the method illustrated was shown capable to data rates of greater than 20 Gbps over distances of greater than 75 cm through two connectors, while meeting specified bit error rate requirements.