Issue link: https://iconnect007.uberflip.com/i/1491842
FEBRUARY 2023 I DESIGN007 MAGAZINE 9 the need to have a firm understanding of the fundamentals of physics and EM effects when designing with shrinking silicon. en signal integrity instructor Rick Hartley and colum- nist Barry Olney team up for a great article about displacement current and its role in EM energy propagation. We have a discussion with Dr. Todd Hubing, founder of LearnEMC and longtime EMC instructor, who points out the advantages and disadvantages of diminutive die, as well as a variety of mitigating tips and techniques for PCB designers and design engineers facing increased signal speeds and rise times. We also have a host of columns from our regu- lar contributors Matt Stevenson, John Coonrod, and Joe Fjelstad, as well as an interview with Jason Sciberras, who discusses the importance of offering optional parts in your bill of materi- als. With the supply chain issues we've had lately, this is quite a timely interview. 'Tis the Season for Trade Shows Speaking of timely, I just returned from IPC APEX EXPO and DesignCon. I talked to a lot of designers, and plenty of process engi- neers who are eager to work with designers to help preclude DFM and DFA issues before they arise. It seems like everyone down- stream from design is realizing the need to keep open lines of communications with the design team. I also talked with designers who are embedded with assembly teams in the name of DFA. Are we all finally starting to communicate? Our Real Time with… IPC APEX EXPO video interviews are available here, and my Design- Con coverage will be published in upcoming issues of Design007 Magazine and Design007 Week newsletter. DESIGN007 Andy Shaughnessy is managing editor of Design007 Magazine. He has been covering PCB design for 23 years. To read past columns, click here. years. But now, with today's chipmakers mak- ing silicon increasingly smaller, things are get- ting, as one designer put it, "ridiculous." Shrinking the signal channel drives up the speed of the signal—as one EE explained, like squeezing an ice cube until it shoots out of your hand. Field effects can't be ignored when the die gets tiny. Designers and design engi- neers must understand EM effects and all the trade-offs involved; they have to know how to propagate each signal without overshoot or undershoot. Material selection plays a bigger role than ever. Seemingly simple concepts such as trace length can have a big impact on the design, and crosstalk is a potential bugaboo, always lurking around the corner. Well, why does silicon keep shrinking? ere are many benefits: Smaller die reduce the cur- rent and use less power, which translates into fewer thermal issues. ey're also cheaper to produce. Like PCB fabricators cutting costs by squeezing more PCBs onto each panel, chipmakers can now stuff more chips onto every wafer. It's a win-win for everyone but the design- ers and design engineers; they must deal with rise times that leave no room for error, even in a best-case scenario. Not only must designers manage signal integrity, but EM effects as well. is is where the world is headed; you don't want to be le behind. So, in this issue, readers will learn the causes and effects of silicon shrinkage, including how to better manage EM strategies and signal integrity, as signal speeds and rise times con- tinue their trek toward warp speed. First, we start with a wide-ranging conver- sation with IPC instructor Kris Moyer, who teaches classes that touch on this topic. Kris explains all the challenges designers face with tiny die, and a few simple techniques that can save designers time and effort—if they know what they're doing. Next, we have a conversation with NXP Semiconductor's Dan Beeker, who points out