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Design007-Feb2023

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46 DESIGN007 MAGAZINE I FEBRUARY 2023 Shaughnessy: What advice would you give designers and EEs who are starting to have EMI and SI issues because of tinier silicon and increased speeds? Hubing: Control your transition times. Use a series resistor for capacitive loads. Use con- trolled-transition-time logic for matched loads. Shaughnessy: Is there anything else you'd like to add? Hubing: Generally—again, in my opinion— shrinking silicon is having a positive impact on both EMI and SI. More is being done with less power and smaller package sizes. If tran- sition times are proactively controlled, newer devices tend to be better options for both EMC and signal integrity. Shaughnessy: anks for your time, Todd. Hubing: ank you, Andy. DESIGN007 Shaughnessy: What is the relationship between smaller silicon and EM fields, and what can these designers do to proactively fight EMI and SI? Hubing: Field coupling directly from an IC is not directly affected by smaller silicon. Field coupling depends more on the currents pulled through the inductance of the lead-frame. Shrinking the features on the silicon can cause those currents to be higher or lower at any given frequency depending on the appli- cation. To protect against future silicon feature-size changes, PCB designers should always proac- tively control the transition times of any signal that could ultimately be the source of crosstalk or radiated emissions. ey shouldn't rely on "slow" devices to meet EMI and SI require- ments. Shaughnessy: If we add increased rise time and faster signals into this mix, how does material and material selection figure into the equa- tion? Do you think OEMs should select their material, or allow the fab to do so? Hubing: I believe laminate selection is strictly an SI issue, and then only for the fastest digi- tal signals. Choosing whether to let the fab- ricator select the laminate depends on the many factors, but, in my opinion, that deci- sion is unlikely to be impacted by silicon shrinkage. Todd Hubing Shrinking the features on the silicon can cause those currents to be higher or lower at any given frequency depending on the application.

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