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36 DESIGN007 MAGAZINE I MAY 2023 is a small fixture consisting of two back-to-back SMA edge-mount coaxial connectors and four 10 milliohm surface-mount resistors. With just metal pieces and resistors, we would expect an R-L-like impedance profile. But the frequency dependency in this case looks as if we had the series resonance of a low-Q bulk capacitor at around 1.5 MHz. How- ever, there is no capacitor in this circuit—not one that could create that low of a series reso- nance. Instead, the reason for the impedance dip is the distributed nature of the resistance and inductance of the ground pegs of the SMA connectors, which interact with the multiple pieces of R-L parallel shunt elements created by the four resistors 2 . 3D effects at relatively low frequencies also show up in wafer-probe PDN measurements 3 . Figure 3 shows a computer rendering of two wafer probes measuring a chip's core power supply across two adjacent power-ground via pairs in a 1-mm array. e inductive coupling between the two loops formed by the probe tips has to be removed from the measured data, either by de-embedding or by calibration. e coupling can be characterized on appropriate calibration substrates. e mutual inductance between the probe tip loops for three differ- ent probe tip geometries is shown in Figure 3b. Note that the mutual inductance has different frequency dependency at low frequencies for the three probe geometries. Conclusion Regardless of the frequency, 3D interac- tions among electrically small features notice- ably impact PI simulations and measurements. DESIGN007 References 1. "The Perils of Right-Angle Turns at DC," by Ist- van Novak, gEEk spEEk, May 14, 2020. 2. "Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range," by Istvan Novak et al., DesignCon 2010, Feb. 1–4, 2010, Santa Clara, California. 3. "3D Connection Artifacts in PDN Measure- ments," by Istvan Novak et al., DesignCon 2023, Jan. 30–Feb. 2, 2023, Santa Clara, California. Istvan Novak is the principal signal and power integrity engineer at Samtec with over 30 years of experience in high- speed digital, RF, and analog circuit and system design. He is a Life Fellow of the IEEE, author of two books on power integrity, and an instructor of signal and power integrity courses. He also provides a website that focuses on SI and PI techniques. To read past columns, click here. Figure 3: a) Wafer probe landing on a via-grid array; b) the mutual inductance between the probe-tip loops as a function of frequency. a b