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42 DESIGN007 MAGAZINE I JULY 2023 need a more efficient solution to support cur- rent and future generations of advanced com- puting products. Merging all the peripheral functions onto the same piece of silicon as that supporting the larger multi-core processor functions has resulted in an excessive increase in silicon area and, for some, unacceptable wafer processing defects. Here's the thing: Defects in the CPU portion of the die are not uncommon. It happens, but when defects occur in any of the peripheral supporting functions, the whole element must be scrapped, even though the multi-core CPU is functioning perfectly. High-Density Semiconductor Packaging Innovation Breaking up the traditional SoC model, sev- eral developers have adopted a heterogenous packaging solution using chiplets, which isn't a package type but part of a packaging archi- tecture. With chiplets, individual die elements can be broken down into smaller pieces and mixed and matched as needed to emulate the multiple function monolithic SoC die. A chiplet is simply a small outline, silicon- based integrated circuit (IC) that contains a specific subset of functionality. e chiplet ele- ments are designed to function in unison with other chiplets, sharing a common platform because the chiplet elements, typical of those illustrated in Figure 1, can be placed very close to one another, minimizing signal path lengths. e shorter path connecting the chiplet ele- ments ultimately leads to enhancing the end product's performance potential. A primary benefit of adopting chiplets is that the cost of wafer fabrication is much lower than the monolithic multiple function die, delivers a higher yield than the single monolithic die variations, and each element can be pre-tested. e flexibility offered by chiplets also provides important design and development benefits. Because they can be customized and upgraded easily, chiplets allow manufacturers to rapidly adapt to changing market conditions or new technological developments. ey also sim- plify the production process by reducing the time and steps required to design and manu- facture complex, application-specific SoCs. So, where does the circuit board designer fit into this emerging package technology swing? Many challenges come with interconnecting chiplets, especially in the context of commer- cial applications and scalability. On the other hand, they offer a promising solution to some of today's most pressing chip design issues. Much like the traditional printed circuit board as the basic interconnect method for electronic products, the heart of the system-in-chip (SiP) Figure 1: Heterogeneous chiplet package assembly example. (Source: Cadence 1 )