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28 DESIGN007 MAGAZINE I AUGUST 2023 Feature Article by Brad Griffin CADENCE DESIGN SYSTEMS Signal integrity (SI) and power integrity (PI) are top priorities for engineers designing today's high-speed, high-density circuit boards, and faster signoff of designs can be achieved by uncovering SI/PI issues early in the design pro- cess, before costly respins are required. ree key issues engineers need to overcome to sign off on high-speed PCB designs include power analysis, serializer/deserializer (SerDes) link compliance, and double data rate (DDR) memory interface compliance. e power delivery network (PDN) must be sufficient, efficient, and stable, and the sig- nal quality must meet memory interface and Three Ways to Improve High-speed PCB Signoff, Part 1 serial link compliance specifications. is arti- cle highlights a PCB design methodology that empowers PCB design teams to create suc- cessful products on time and on budget with- out waiting for SI and PI specialists who may not be readily available. Design Analysis Frameworks ere are several important frameworks to consider when designing PCBs (Figure 1). e design begins with the schematics, fol- lowed by the layout, and then, late in the layout phase, a detailed analysis is done to ensure the layout functions properly. During the design Figure 1: Design analysis frameworks.

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