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34 DESIGN007 MAGAZINE I SEPTEMBER 2023 Article by Brad Griffin CADENCE DESIGN SYSTEMS Editor's note: Part 1 of this article is available here. Another challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appro- priate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Alle- gro schematic constraint manager (system capture). e preliminary constraints and schematics flow is illustrated in Figure 1. As the design progresses with final decisions on stackup and material selections, these con- straints can be adjusted. With the schematics phase finished and the layout phase in progress, the next challenge is compliance with specifications. Specs are dependent on the technology—PCI Express (PCIe), USB, etc.—and, because each one has its own requirements, this can be a complicated process. During this analysis, it is important to make sure the correct transmitter and receiver IBIS-AMI models are being used. For the channel, Cadence tools can be used to accurately model the channels and address specifications. is is done by using the board file created by the layout designer, selecting Three Ways to Improve High-Speed PCB Signoff, Part 2 Figure 1: SerDes constraints and schematics workflow using the sweep manager utility in Sigrity Topology Explorer (TopXp).

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