Issue link: https://iconnect007.uberflip.com/i/1507356
40 DESIGN007 MAGAZINE I SEPTEMBER 2023 ensure the channel is meeting DDR specifica- tions. Again, this flow enables the PCB designer to be less dependent on the SI expert by doing much of the validation independently. en, for the final check, the entire block is analyzed in a full-wave 3D simulation using the Clarity solver to make sure every detail is cap- tured, and the DDR compliance analysis check is run (Figure 7). For the compliance analysis, the designer doesn't need to know all the details discussed earlier, as the simulation workflow provides all the results for the specific protocol that has been selected. If the design passes this flow, the designer can be confident that the board works properly. Board Design Example is example describes a real-life PCB exam- ple that demonstrates how Cadence's Allegro/ Sigrity/Clarity design flow streamlines the design process. Figure 8 illustrates the con- straint phase of the design. e design is in the schematic phase and the PowerTree file is used to show the power rails and validate that they have been set up correctly. During this phase, some iterative DDR simulations are also run to ensure that the first-pass constraints are correct. e same process is used to run SerDes simulations and ensure the right dielectric has been chosen, the stackup is right, etc. In parallel, either with or without the help of an SI expert, the designer Figure 6: Interconnect model extraction is used to validate waveforms and run DDR analysis. Figure 7: In the final design check, a DDR analysis is performed on the entire block using the Clarity full-wave 3D electromagnetic solver.