Issue link: https://iconnect007.uberflip.com/i/1507356
SEPTEMBER 2023 I DESIGN007 MAGAZINE 37 to run the iterations again. is also enables designers to fine-tune the preliminary con- straints during the layout phase and update them to values that can be used on other sig- nals. In addition to traditional SI issues usually addressed during the schematics and layout phases, the nature of DDR makes it suscep- tible to three additional challenges that must be addressed: simultaneous switching noise (SSN), via-via crosstalk, and JEDEC standard compliance. Cadence soware empowers the PCB design team to address these issues when SI expertise is not available. SSN Challenge In SSN, the transistor drives the output of a single bit, drawing power from the voltage rail as needed and dumping it into the net. e behavior of this transistor is traditionally cap- tured in an IBIS file or analysis. With DDR, it is possible for multiple nets to toggle simul- taneously and the transition between states will have a high current rate-of-change (di/ dt) requirement that affects the voltage level, which in turn affects the transition (Figure 4). Two models are critical for accurately model- ing SSN: a power-aware IBIS model and an accurate model of the PDN. Figure 3: TopXp topology sweeps are optimized in the schematic constraint manager. Figure 4: Multiple nets can toggle simultaneously, having a high di/dt requirement that creates interdependency between the voltage level and transition.