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32 PCB007 MAGAZINE I OCTOBER 2023 been modified over the years to perform many different requirements. Figure 4 shows a close- up of 1 µm and 1.5 µm t/s in the organic ABF film on a glass panel. As shown in Figure 5, typical Cu pillar flip- chip bonding has a die pad pitch of 100 µm with an I/O density of 105 I/O mm 2 . TSMC's integrated fan-out (InFO) has a die pad pitch of 55 µm with an I/O density of 314 IO/mm 2 . [3] To further decrease interface pitch, new inter- connect technologies were developed, such as Intel's EMIB (embedded multi-die inter- connect bridge), which can achieve a die pad pitch of 45 µm with an I/O density of 492 IO/ mm 2 . e first-generation Deca M-Series, with a planarized structure above the encapsulated active die coupled with the patterning technol- ogy, achieved the same 45-µm interface pitch as compared to EMIB, without the need for com- plicated bridge chips embedded in substrates. With the new Gen 2 technology, this die pad pitch can be further scaled to 20 µm, thereby achieving a more than 5X increase in I/O den- sity of 2518 IO/mm 2 . Gen 2's advanced LDI and automatic optical inspection (AOI) equip- ment, combined with the patterning technol- ogy, provides a path for the ultra-high-den- sity die pad pitch and RDL density required for chiplets and advanced heterogeneous inte- gration. rough-glass-vias (TGV) and copper pillars are needed for interconnects and ther- mal heat spreading. Figure 4: Next-generation high aspect ratio 1 µm RDL of organic film on glass for HPC development at Georgia Tech.