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34 PCB007 MAGAZINE I OCTOBER 2023 Summary A 650 mm x 650 mm panel-level approach to fan-out (PLFO) technology is being uti- lized, which enables assembly of four 300-mm round or 300-mm square fan-out subpanels on a carrier panel. is technology enables the re- utilization of the reconstitution and die/pack- age-level processing equipment, focusing the panel processing where the greatest cost ben- efit can be achieved in the redistribution layer process. e use of a carrier panel minimizes the warpage, permitting implementation of more RDLs without impacting processabil- ity. e flow is performed on the smaller form factor, minimizing die-shi considerations on the large panel. e same panel equipment and infrastructure can also be used for chip- last PLFO or high-density, high-quality core- less substrates. Process flow details will be shared based on a PLFO pilot line in use now. e new SEMI standard for large-panel arrays looks to lower the cost and improve perfor- mance and reliability for multi-arrays die sub- strates 5 . Glass packaging is emerging as a next-gen- eration packaging platform beyond organic and silicon packaging. It has been developed in both chip-first and chip-last 2.5D and 3D architectures. Georgia Tech and its industry partners have developed all the building block technologies necessary to manufacture. PCB007 References 1. HDI HANDBOOK, Chapter 3, by Happy Holden. 2. "Next Steps For Panel-Level Packaging," by Mark Lapedus, Semiconductor Engineering, Dec. 20, 2021. 3. "Glass Panel Packaging as the Most Leading- edge Packaging: Technologies and Applications," by Rao Tummala, Bartlet Deprospo, Shreya Dwara- kanath, SMTA Pan Pacific Symposium, Hawaii, 2020. 4. "Large-panel fan-out perspective on cost, yield, and capability," by Clifford Sandstrom and Robin Davis, Chip Scale Review, November 2022. 5. "A Hybrid PLP Technology Based on a 650mm X 650mm Platform," by Eoin O'Toole, Semiconduc- tor Engineering, July 25, 2023. Further reading "600MM Wafer-Level Fan Out on Panel Level Processing With 6-Sided Die Protection," by Jacinta Aman Lim and YunMook Park, Proceedings of the International Wafer-Level Packaging Conference 2020, San Diego. Happy Holden has worked in printed circuit technology since 1970 with Hewlett- Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. To contact Holden or read past columns, click here. Figure 5: Comparison of interface pitch between different interconnect technologies and the M-Series from Deca. (Source: Deca Technologies, Inc. 4 )