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Design007-Jan2024

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46 DESIGN007 MAGAZINE I JANUARY 2024 chips in a dense printed circuit board, we end up with a lot of perforation due to the many antipads around vias that do not connect to the particular plane. is becomes obvious under the cores of big chips, where alternating power and ground through-vias perforate the planes. If we do not consider the slanted sidewalls, we may end up with a too optimistic design. e illustration in Figure 4 is reproduced 4 . It shows the simulated voltage drop on the power plane of a high-current CPU rail, assuming vertical sidewalls and the more typical 60-degree side- walls. e etch factor alone results in a 10% increase of end-to-end resistance, on top of the impact of the perforation itself. Summary We need to be aware of the basics of PCB fabrication and assembly because they have an impact on the high-speed, power integrity, and thermal performance of our boards. DESIGN007 References 1. "Increasing Broadband Interconnect Character- ization," EDICON 2018. 2. "A Case Study in the Development of 112 Gbps- PAM4 Silicon and Connector Test Platform," Design- Con 2021. 3. "Mind Your Units," Printed Circuit Design and Fab, Circuit Assembly, December 2023, p. 56. 4. "Etch Factor Impact on SI & PI," DesignCon 2019. Istvan Novak is the principal sig- nal and power integrity engineer at Samtec with over 30 years of experience in high-speed digital, RF, and analog circuit and sys- tem design. He is a Life Fellow of the IEEE, author of two books on power integrity, and an instructor of signal and power integrity courses. He also provides a web- site that focuses on SI and PI techniques. To read past columns, click here. Figure 4: Effect of etch factor on DC resistance and loss (reproduced 4 ).

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