Issue link: https://iconnect007.uberflip.com/i/1514189
62 DESIGN007 MAGAZINE I JANUARY 2024 you're testing areas of the circuitry. You look around at the different control ports, and if you want to utilize things like boundary scan, make sure the five key pins have some kind of access, whether it's going through a header or a bed of nails, where you can access that point to utilize the boundary scan capabilities on the board. en you'll have that controllability in utiliz- ing test tools. Also, be sure to have access to allow for enough power and ground points on the board so you have a balance and you don't have ground bounce. If you're looking at ICT, flying probe, or anything with a bed of nails, you want physi- cal access so you don't have to have the big 0.032" points. Differ- ent probing technologies allow you to utilize smaller center-to-center spacings. You can use a through-hole device as a test point on a net; just utilize an unmasked via and call it a test via. Normally on a bed of nails, you don't want to go below 0.018" to .020" in diameter; you want to stay in 0.039", 0.050", 0.075", or 0.100" center-to-center spacing. When you look at testability, controllabil- ity, having enough power and ground points on the board, and then the physical access, you realize that DFT could be setting up your test strategy. I know I will be looking at these bypass caps with AOI, and AOI or testing will be looking at this, so I don't need to have test points all over that part of that circuitry. If you're in RF, or even just high-speed digital, you might say, "I can't have test points hang- ing off that because there are a whole bunch of RCLs hanging off that location." Well, what can we test, and how do we test that high- speed portion of that board through a black box when not everything is high speed? en you can say, "I'll test the board using boundary scan," and if you have these things chained together, you know you're not drop- ping test points on the CCA. Designers should understand a good amount of the test strategy and how we run a test service. A lot of times, designers are not looking at that, and it's not really their fault. ey're not building the board, or testing it in a production environ- ment. You have to make the test stable, reli- able, and robust enough that you can handle multiple boards if you are doing production over 100 or 1,000 pieces. How does test change with production volumes? If you're getting into tens of thousands of pieces, then you need bigger test tar- gets, and you have to allow for panelization. e panel layout is something that a lot of people don't think about, and that's not always the function of the designer. at's the function of the manufacturer. Designers should be thinking about not only how man- ufacturers will build the board, but also how they're going to test the board. When all the boards on your panel are not facing the same direction, you will create a lot more challenges than solutions. You have to have some control- lability on that. You're really buying the panel, right? Exactly. If you're a designer with an OEM look- ing at contract houses, you should know going into it what their test methodology is and not just throw it over the wall. Because if a contract manufacturer has an old Z1800, that will use a different test strategy than somebody who has a new Keysight 3070. If you have more and newer tools, you have more capabilities. ere are also limitations with flying probe DFT, where you will be probing on a joint. You need to know how you'll access these points and what your probing angle is. If you're com- ing straight down on a test target that's eight degrees, that will be handled a lot differently than coming down at zero degrees. e OEMs There are also limitations with flying probe DFT...