Issue link: https://iconnect007.uberflip.com/i/1518649
22 DESIGN007 MAGAZINE I APRIL 2024 Stacking microvia holes directly in line with one another will simplify circuit routing dur- ing the CAD development process, but addi- tional plating process steps to fill and planarize the resulting via cavities will impact fabrication throughput. When implementing vertically aligned microvias, each stage of the lamina- tion sequence will require that the depression in the center of the microvia be plated flush with the surface of the copper conductor's sur- face before lamination of the next circuit layer. Circuit fabricators note that providing a stable copper-to-copper interface between the filled microvia levels may be at risk when subjected to long-term physical or thermal stresses. When clustered together (fine-pitch array type semiconductor package interconnect, for example), thermal cycle testing of the in-line, vertically stacked microvia holes exhibited positive results. Note: Studies conducted by Summit Inter- connect found aer extensive thermal test evaluation that the clustered, three-stack direct via-to-via interface format, typically required for fine-pitch array configured components, proved to be reliable. Although the staggered three-level microvia will require slightly more surface area than the vertically stacked alternative, circuit board fab- ricators prefer the offset microvia option for circuit interconnect when vias are distributed randomly on the circuit board because the multilayer lamination sequence requires fewer process steps. With the microvias arranged in the staggered format, the copper fill operation is eliminated, saving both time and process complexity. For both vertically stacked and staggered via-in-land component attachment sites on the circuit board's outer layer(s), an addi- tional copper plating step will be necessary to fill microvias flush with the land pattern's surface to negate potential void formation in the solder interface during assembly process- ing. High Density Conductor Routing Conductor routing protocols must be estab- lished in advance. Adapting blind and buried microvia holes and furnishing pre-defined routing channels will help the circuit board designer to facilitate efficient routing of these oen very fine-pitch and array terminal con- figured semiconductor packages. To aid the designer in establishing copper conductor width and spacing for circuit routing, IPC- 2226 has defined three HDI circuit board com- plexity levels (Table 1) for both external and internal locations. The space separating via lands, microvia lands, and/or component attachment lands is referred to as channel width. e channel widths for routing array-configured semi- conductors can easily be mathematically cal- culated using the terminal pitch (center-to- center distance), overall land pattern size, and the width and spacing established for conduc- tors. is will provide the maximum number Figure 2: Comparing a staggered to a vertically stacked microvia interface.