Issue link: https://iconnect007.uberflip.com/i/1520213
40 SMT007 MAGAZINE I MAY 2024 would like to put more chips into a single pack- age and have them talk to each other with high bandwidth, low latency, and low-energy inter- connects. at goal is driving emerging packag- ing technologies to higher interconnect densi- ties, more routing layers, and larger body sizes. Ever since semiconductors were developed, we've used the thought pattern of making bigger monolithic chips. Why the change? For a long time, the fundamental idea was that we could get more performance out of larger dies at the most advanced technology node. Fabricating all parts of a chip at the most advanced node is getting very expensive and has major yield challenges, so this drives us toward smaller die sizes. Additionally, we can partition the chip such that some parts that don't scale well can remain in an older technol- ogy node. at's a very natural fit for chiplet architecture. Aren't we starting to use a building block approach? Yes, and that's another great advantage in a few different ways. Starting from one product, we can use this building block approach to make different part numbers and define the right- sized chip for a particular application. It also opens the gateway to creating heterogeneous chiplet architectures for targeted applications for which creating an ASIC would be simply too expensive. Chiplets allow cutting-edge manufacturing techniques to be used only for the pieces that really matter, as opposed to the entire monolithic chip. at's right. In fact, that is another very strong moti- vation for the chiplet par- adigm. It allows the lead- ing-edge nodes to focus on the logic and the compute parts, for example. Many of the other parts of a system-on-chip (SoC) don't scale in the same way, so there's no real incentive to tape out those portions in the lead- ing node; they may actually perform better at an older node. In general, we call this breakup of a monolithic chip into chiplet components "disaggregation." One example might be that you need to include a USB I/O interface; that subsystem can be added through a standard chiplet part using an older fab capability. Exactly. We're currently looking at how we can optimize this disaggregation, or "chiplet factoring," for an AI chip applica- tion. We're working on questions like, "How would we break up the fundamental compo- nents of an SoC into chiplets, and what is the optimal technology node for each of these pieces?" Your recent presentation at the IMAPS conference makes the point that AI and ML are driving this rapid pace of hardware development. Tell me more about that. On the one hand, the compute and memory demands of AI are growing exponentially as AI has become a pervasive workload. On the other hand, we've encountered the stalling of traditional scaling; we can't get as much com- pute power growth through scaling as we could count on in the past. Chiplets are a way to meet these very high demands.