Issue link: https://iconnect007.uberflip.com/i/1520701
MAY 2024 I DESIGN007 MAGAZINE 17 Kelley: In fact, in the digital world, when you get below, say, 0.003 for a Df, conductor losses are a bigger factor. When I worked at a CCL manufacturer, we ended up building PCB- level insertion loss test vehicles, and back-cal- culating out Df values based on insertion loss measurements, accounting for both dielectric and conductor losses. It's very difficult to mea- sure Df on laminate at very high frequencies when the dielectric itself is extremely low loss. When the dielectric losses are that low, your measurement error can be almost as large as the loss you're trying to measure. Moyer: Our old friend Nyquist is coming back in. Basically, Nyquist was about statistics in order to have successful measurement of an unknown signal. e measurement had to be at least 10X the frequency, magnitude, or ampli- tude. You basically had to have 10X better mea- surement building it than what you were try- ing to measure. Otherwise, your measurement was basically of the noise in the system doing the measuring. at is measuring or characterizing the Dk and Df, which is different than measuring the thicknesses of the dielectric. How are those measured, and are the tables listed on a sup- plier's site? Another point on board fabrica- tion that designers do not understand well is regarding those construction tables. ose are pre-laminate thicknesses. I've seen so many designers say, "I need 5.2 mils," and put all the layers to 2.6 mil, to get 5.2 mils and then won- der why they get 4.7 or 4.8. For pre-laminate thicknesses, that's yet another conversation you need to have with your fabricator. Shaughnessy: This has been a really interest- ing conversation. I expect we'll see more and more companies using FR-4 flavors in high- speed and RF designs. Moyer: Absolutely. I'm teaching this in my class. Shaughnessy: Kris, Ed, thank you both for your time. Kelley: I enjoyed it. ank you. DESIGN007 The Semiconductor Industry Association (SIA), in partnership with the Boston Consulting Group (BCG), released a report on the global chip sup- ply chain that projects the United States will triple its domestic semiconductor manufacturing capac- ity from 2022—when the CHIPS and Science Act (CHIPS) was enacted—to 2032. The projected 203% growth is the largest projected percent increase in the world over that time. The study, titled "Emerging Resilience in the Semiconduc- tor Supply Chain," also projects the U.S. will grow its share of advanced logic (below 10nm) man- ufacturing to 28% of global capac- ity by 2032, up from 0% in 2022. Additionally, America is projected to capture over one-quarter (28%) of total global capital expenditures (capex) from 2024-2032, ranking second only to Taiwan (31%). In the absence of the CHIPS Act, the U.S. would have captured only 9% of global capex by 2032, accord- ing to the report. While the report finds investments from the industry—facilitated by CHIPS incentives—are on track to reinvigorate semiconduc- tor manufacturing in America and reinforce U.S. chip supply chains, it also identifies policy actions that will further strengthen sup- ply chains, support R&D and chip design, grow the semiconduc- tor workforce, and ensure CHIPS delivers maximum benefits to America's economic and national security. (Source: SIA) America Projected to Triple Semiconductor Manufacturing Capacity by 2032, the Largest Growth Rate in the World