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92 PCB007 MAGAZINE I JULY 2024 With channels (slots) formed from both sides, the 3D vertical traces provide greatly increased density without sequential lamina- tions. Replacing larger through-hole with slots provides better power integrity for new power- hungry chips while lowering inductance and capacitance for improved signal integrity. The Channel or Slot e all-important step of metallizing and plating the typical 0.3-mm blind slot (Figure 7a) is shown in the column of various depths and lengths (from depths of 0.47 mm to 1.23 mm and lengths of 0.6 mm to 1.8 mm). Some of the smaller aspect ratios have insufficient chemical exchange but the majority have excellent chemical exchange for normal plat- ing baths. e new alternative drill/router bits have successfully created channels of 0.1 mm with straight walls and no burring. Fabrication Process e VeCS fab process starts with a conven- tional through-hole multilayer. e process has eight steps: 1. Create slot 2. Plate slot 3. Alignment in BGA pin field 4. Resin fill PR slot and PR stencil 5. Drill CR slots 6. If vertical traces are used, drill BR slots 7. BR/CR stencil 8. Resin fill BR/CR slot First, aer drilled vias are completed, the pri- mary cross-rout (CR) slots are put in. Here, a special drill/router bit uniquely suited for this operation is used. Much work and experimen- tation were conducted to perfect an ideal drill/ router bit for this task. en metallization and copper plating are performed. Resin is now used to fill the CR slots. Curing is the important step of cross-routs that create the vertical inter- connects. If vertical traces are used, drill/rout out the back-rout (BR) slots. en, selected vias and slots are resin-filled and cured. In step 7, for pattern plating, the normal process resumes of imaging, plating, stripping, and final etching. In the final panel, the board would be solder masked, with any final finishes and fabrication. Figure 7e shows a 3D cut plane view and the inner layer connection and surface connection views for VeCS. Integrated Mesh Power Systems (IMPS) In the late 1990s, thin-film multichip mod- ules (MCM-D) were to be the salvation of the interconnect industry. Fine-line lithography would allow miniaturization with ease. Unfor- tunately, the four or five metal layers to which integrated circuits were wire-bonded proved to be too expensive compared to printed cir- cuit multilayers and the emerging silicon inte- gration on ball grid arrays. IMPS technology was created to reduce the cost and metal layers on thin-film and ceramic multichip modules. e IMPS topology can reduce the metal layers to only two or three. is results in a substantial cost reduction and simplification while not affecting electrical performance. Background: IMPS e scientists at the High-Density Elec- tronics Center (HiDEC) of the University of Arkansas, Fayettville, invented IMPS in the mid-1990s. IMPS allows a low inductance co- planar power and ground distribution, as well as dense, controlled-impedance, low crosstalk signal transmission in only two wiring layers. Figure 1 3 shows the basic IMPS technology. e conventional metal wiring topology is to have signals on one metal layer and power and ground on separate metal layers. e resulting usage of these expensive metal layers is quite low. Signal layers may have only 50–60% utili- zation and power/ground layers only half that amount when either the coarse mesh or fine mesh is utilized. ey may be made smaller (if signal losses can be tolerated), but the spacing cannot. High-speed, fast rise-time signals are sensi-