Issue link: https://iconnect007.uberflip.com/i/1527613
20 DESIGN007 MAGAZINE I OCTOBER 2024 e sequence in which the circuit board lay- ers are assembled (signal, power, ground, etc.) is a key factor that will affect signal transmis- sion performance. In addition to performance concerns, controlling fabrication costs should be a priority as well. Layer count and the method selected for interconnecting between circuit layers, for example, will have a signifi- cant influence on controlling process complex- ity. Implementing blind microvia technology for layer-to-layer interconnect will enable sig- nificantly greater circuit routing density, but the build-up process has a substantial impact on the manufacturing complexity since it will affect the number of lamination cycles. Any layer on which a microvia begins requires a sub-construction with a perfectly aligned land pattern to complete the layer-to-layer via interface. A concern is that during each lami- nation cycle, the core materials are subjected to repeated exposure to elevated temperatures and high physical pressure that can contribute to material decomposition. Controlling HDI and UHDI Fabrication Cost e printed circuit board complexity level is determined by the number of signal and power/ground layers needed for intercon- nect. By adopting finer lines and spaces, small microvia holes, and innovative multilayer methods, the PCB designer will be able to overcome the many interconnect challenges posed by the newer generation semiconduc- tors. When defining the complexity level for the HDI or UHDI circuit board, the designer will first establish a criterion for fabricating the circuit board. is will include the board out- line and thickness limitation. In regard to con- trolling the specified circuit board thickness limit, a clear objective must be established to identify the number of circuit layers that are to be dedicated to signal routing and the number of layers reserved for power and ground distri- bution. While power and ground may require only two circuit layers, estimating the required number of signal layers will be determined by the component density and interconnect com- plexity. When assessing printed circuit board design complexity, first consider the component area and board area ratio. If the surface area for component interface is restricted, it may jus- tify adopting HDI multilayer fabrication. To assure a successful outcome for the HDI circuit board, it is important that the designer recog- nize the manufacturing process complexities and associated cost impact when implement- ing the more sophisticated fabrication proce- dures. Conductor routing protocols must be established in advance. e space separating via-hole lands, microvia lands and/or compo- nent attachment lands is referred to as "channel width." e channel widths for routing array- configured semiconductors will be mathemat- ically calculated using the terminal pitch (cen- ter-to-center distance) and the size of the land pattern. is provides the maximum number of conductors that can be routed between each " In addition to performance concerns, controlling fabrication costs should be a priority as well. "