Issue link: https://iconnect007.uberflip.com/i/1529118
22 DESIGN007 MAGAZINE I NOVEMBER 2024 • Try to keep all polarized components ori- ented the same way for assembly efficiency. • Do not place components closer than 50 mils to edge of board to optimize the assembly process and minimize handling issues. • Do not flood over through-hole power pins with copper. ermal reliefs should be added for assembly. General Design Practice • Placement of components is typically performed in the following order: active components, high-frequency caps, series resistors, pull-ups/pull-downs, and bulk caps. • When possible, maintain a minimum spacing between vias to avoid creating "gang voids" or fences in planes and enable routing between the vias. Placing vias on a grid helps accomplish this; the larger the via grid the better. (50 mils, 40 mils, 1 mm, 0.8 mm). • Place metric-pitched BGA parts on a met- ric grid, along with all passive components and via-fan-out for consistency. • Add ground stitching under thermal pads and try to avoid paste in mask apertures if possible. Tent opposite of vias or use 8–10 mil via drills to minimize the amount of paste that can wick through the via. Or better yet, use solder mask dams around the vias under the part to avoid special processes and increased costs. • All BGA balls collapse. Non-collapsing BGA balls are created by the PCB librarian by solder mask defined pads or making the pad size larger than the ball. Signal Integrity • On controlled impedance circuits, as the dielectric thickness increases between the trace and its reference plane, the trace widths should be increased to compensate for this increased dielectric to maintain the target impedance. • Place RF GND stitching vias center-to- center spacing per frequency require- ments. • Always place GND stitching vias near hi- speed differential transition vias. If you must place ceramic or thin film compo- nents near an edge, try to keep the long axis of the part parallel to the edge rather than perpendicular, to reduce the risk of cracking the part. For non-lossy RF trans- mission lines use 14-mil traces or wider to increase capacitance. is also helps when the trace enters/exits passive component pads, and this reduces the parasitic capaci- tance. • When placing split/mixed technology boards, isolate analog ground vs. digital ground and keep all circuits that refer- " When possible, maintain a minimum spacing between vias to avoid creating 'gang voids' or fences in planes and enable routing between the vias. "