Issue link: https://iconnect007.uberflip.com/i/1529118
NOVEMBER 2024 I DESIGN007 MAGAZINE 23 ence either ground within specific ground domain. Do not cross over ground domain splits without a plan for return path. • Add peripheral ground via stitching and ground via stitching in open areas of board to minimize EMI. • Solder-mask can affect the impedance of high-speed transmission lines. • Target 2x trace/trace minimum spacing to avoid crosstalk. 3x spacing is even better, and 5x spacing will eliminate any potential for crosstalk. is is dependent upon the dielectric materials, frequencies and envi- ronments. • A guard trace tied to ground may be desir- able to shield the edges of high speed (fast edge rates) signals if they are close to a board edge. • High impedance (think input) traces should avoid high energy traces and planes (switching nodes, inductors, FETs, etc.). • High impedance RF signals may need voids under pads to maintain uniform impedance matching. • Analog/power/digital separation may call for dedicated return path reference planes to prevent GND plane mixing of signals. Add a gang void or fence around these vias in all planes that the vias go through. • When possible, maintain a minimum spacing between vias to avoid creating gang voids in planes and enable routing between the vias. Placing vias on a grid helps accomplish this, the larger the via grid the better. (50 mils, 40 mils, 1 mm, 0.8 mm) Power Supplies • Place highest frequency decoupling bypass capacitors close to the IC's power pins and minimize distance to reduce inductance. • Never route signal traces under a switching power supply. • Try to minimize the inductive loop between the input/output of a switching power supply. • A ground plane greater than 10 mils to a power plane on adjacent layers of a PCB stackup will greatly increase the embedded capacitance and is always a good practice, especially where decoupling or current carrying capacity is a concern. • A standard 10 mil via can produce approxi- mately 1.5 amps of current carrying capac- ity. • Raw input voltages should typically use some sort of protection coming into the board (protection diodes, fuses, filters, etc.). • Add test points to power rails and GND nets and label with silkscreen to make debugging more efficient. • Use wider/heavier copper when achiev- able. • Ground/reference planes should extend beyond the power planes by 3x the dielec- tric thickness to reduce "fringing," as columnist Barry Olney discusses in this Design007 column from a few years ago. Scott Miller is chief customer officer at Freedom CAD Services and the author of The Printed Circuit Designer's Guide to Executing Complex PCBs. Scott Miller