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44 SMT007 MAGAZINE I DECEMBER 2024 different types of chips (e.g., logic, memory, sensors) within a single package. It enables the creation of multifunctional devices that are both powerful and small, ideal for IoT applications. Flip-chip and wafer-level packaging offer higher interconnect density and better elec- trical performance compared to traditional wire bonding. ey are crucial for high-perfor- mance applications and are also adaptable for smaller devices. For IoT devices, the focus is on reducing size and power consumption. Advanced packaging technologies are enabling the production of ultra-small, energy-efficient chips that can be embedded in a wide range of devices. ese advancements are helping the semi- conductor industry balance the need for both high performance and miniaturization, driving innovation across various applications from consumer electronics to industrial IoT. FOWLP and FOPLP are two packaging technologies gaining traction recently. What are some of the drivers and challenges for these approaches? With the surge in data-hungry applications like AI, where chips are larger, fan-out panel- level packaging (FOPLP) technology is gain- ing renewed attention. By utilizing larger pan- els instead of wafers, such as 600-mm square panels, compared to traditional 300-mm round wafers, manufacturers can achieve significant cost reductions and boost production efficiency. Packages can be built in two ways. A foundry must decide whether to use the chip-first or chip-last method. e c h i p - f i r s t / R D L - l a s t approach reduces pro- cess steps and produc- tion costs. Whereas a c h i p - l a s t / R D L - f i r s t approach reduces risk of damaging an expen- sive AI chip since its pads and RDLs are inspected and checked. When a bridge is used to connect mounted dies, both methods will probably be used: chip-first for the cheapest bridge and chip-last for the AI die. Moving to panel-level packaging raises sev- eral challenges, some of which are associated with the transition to panels, while others are also relevant to wafer-level packaging (WLP), but with amplified effects. One of the primary challenges is die shi (bridge), which can occur during the manufacturing process and lead to misalignment, affecting the overall per- formance of the package. Warpage of panels aer molding and redis- tribution layers (RDLs) is another major issue. Warpage can cause difficulties in han- dling and transporting the panels, misalign- ment in the bumping, and potential defects. Due to the large size of the panels, handling and transport are challenging. Ensuring uni- formity across the entire panel, especially for processes like coating, sputtering, and plat- ing, is also critical. Looking ahead, what do you envision as the next major breakthrough in semiconductor packaging, and how might it redefine the way we think about electronics design? Co-packaged optics (CPO) is an innovative technology that integrates optics and silicon in a single package. It addresses bandwidth and power challenges in next-generation data centers and cloud infrastructure. CPO com- bines expertise in fiber optics, DSP, switch ASICs, and advanced packaging and testing,