Issue link: https://iconnect007.uberflip.com/i/1530269
12 DESIGN007 MAGAZINE I DECEMBER 2024 instances of unbalanced Z-axis and still meet bow and twist constraints. Furthermore, many of the ultra-thin dielectric layers used in HDI/ UHDI are just resin-coated copper without any reinforcement, so CTE/FA can be more of an issue. What are some of the trade-offs—DFM, SI, materials, etc.—that designers need to navigate when designing a stackup with advanced packages? I touched on this in the last question. When it comes to DFM, since the layers are added one at a time and oen those layers don't have reinforcement materials, there is the potential for more layer-to-layer misregistration during lamination. From an SI point of view, there is now plating on all layers and the tolerance on the plating will need to be considered on impedance calculations. How does our choice of via construction come into play? e various via types all have their own trade- offs. Stacked vias, for example, take up less board space but require the extra process steps of plug, cap, and planarize in order to make the layer-to-layer connection. Staggered vias, on the other hand, do not require the extra pro- cess steps but may have entrapped contami- nants in air voids that could lead to other issues during assembly if there is not enough resin in the layer to fully fill the via during lamination. As chip packages shrink, they create all sorts of follow-on issues such as energy concentra- tion, smaller vias, etc. What other challenges does this create? e biggest challenge with very small package sizes is the need to use much thinner copper to fabricate the necessary feature sizes. is cre- ates a snowball effect; when the same surface finish used for thick coppers is used on thin coppers, this can lead to increased impact on skin effect for signal propagation. Decreased adhesion if surface roughness is reduced and less margin for over current/thermal issues is another issue that happens with the use of thinner coppers. ese are just a few of the issues faced. What DFM issues are fabricators look- ing for in this situation, and what can designers do to stay ahead of the game? As I mentioned, the need for thin cop- pers and microvias puts the fabricator on the lookout for several issues. First, has the stackup and increased layer-to-layer misregistration been considered? Second, using very thin coppers limits the amount of oxide treatment/surface roughness that can be added to the copper, so the resin-to-cop- per adhesion will not be as robust. ird, has the designer accounted for plating on the inner lay- ers needed for sequential lamination? Fourth, has the stackup/material selection accounted for the need for multiple lamination cycles? ese are just some of the big hitters that fabricators are looking for with HDI/UHDI designs. Is there anything else you'd like to add? While the challenges presented here do make HDI/UHDI a bit more complex than traditional designs, the benefits of reduced package/prod- uct size, increased design capability, and need to use smaller package sizes makes the reward worth the risk. With the proper knowledge, training, and partnership with your fabricator, any designer can create a successful, robust HDI/UHDI PCB design. DESIGN007