Issue link: https://iconnect007.uberflip.com/i/1530269
18 DESIGN007 MAGAZINE I DECEMBER 2024 • Use the smallest trace width as a "grid" set- ting for trace and space. (G) • Approximate space you'll need to route the board: [(G)•(# SP)] + [(V)•(# PP)] = Approximate routing space needed (RS) Number of layers needed for routing: (RS) / (AB/2) = Approximate number of internal layers Spacing between layers: The space between layers can be either core or prepreg. No, the spacing between layers of copper will contain resin and reinforcement. ese are determined by the layer stack requirements to attain the electrical specifications needed for the design. Either core or prepreg is used as needed. By definition, core material usually has cop- per on both sides, and the resin is fully cured, oen referred to as copper-clad laminate (CCL). Prepreg has no copper, and the resin is partially cured. Stacked vias: Avoid stacked vias if possible and choose staggered instead. Yes, this is true. Each time you add a stacked via to the center core of a board (1, 2, 3, or more), it is the equivalent of starting the fabri- cation process from the beginning. Resin slips a bit each time you heat and press the layers together. Alignment of the vias is very difficult to accomplish. ere are new processes that have been explored in 3D printing that will allow better alignment of these types of vias. ere are very few companies right now who can do it and it's not cheap. ere are many more design rules than what has been covered here. ey continue to expand to include newer "rules" for develop- ing our PCB designs. What is today's bleeding- edge technology will become standard some- time in the not-too-distant future. erefore, it is imperative that designers keep up with what's happening. DESIGN007 Cherie Litson, MIT CID/CID+, is the founder of Litson1 Consult- ing and an instructor at EPTAC and Everett Community Col- lege. She has more than 30 years of design experience and has been an instructor since 2003.