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74 PCB007 MAGAZINE I AUGUST 2025 Solution flow is reduced as hole diameters decrease and board thicknesses increase. Solu- tion flow can decrease sufficiently to cause voids. Another issue that leads to voids is hydrogen gas bubble entrapment. The gas bubbles from hydro- gen gas generation are a by-product of the elec- troless copper deposition reaction. The air bubbles become entrapped when the solution movement is unable to displace the bubbles. A companion cause of gas bubble entrapment is the surface energy of the electroless copper plat- ing solution. Basically, the gas bubbles tend to localize in low-energy areas of the solution. This is referred to as high surface tension. By lower- ing the surface tension, you can reduce the size of the bubble, making it easier to dislodge the bubble from the hole. A key aspect of minimizing defects due to gas bubbles is to create an environment whereby gas bubbles formed are much smaller and thus more easily dispersed. This includes engineering the electroless copper process to reduce bubble size and reduce surface tension (thereby increasing surface energy). In doing this, you can minimize the size of the bubbles before they coalesce into larger ones. Figure 2 shows a high aspect ratio hole processed through an optimized electroless copper process. The printed wiring board industry has typically addressed small hole voiding in several ways, some of which can adversely affect reliability, including: • Double passing through the electroless copper solution • Increased work bar agitation • Angling the panels in the plating rack to facilitate gas bubble removal • Vibration agitation on the flight bar • Bump agitation accomplished with the use of a lifter and cam assembly located beneath the flight bar. The lifter provides one bump per agitation stroke cycle • Increased panel spacing between the panels in the rack to facilitate solution flow In most cases, these solutions solve small-hole voiding. However, beware of the detrimental effects when implementing these options. Of grave concern is the option to "double-pass" PWBs with small-diam- eter vias through the electroless pro- cess. Fabricators claim that by doing so, they can eliminate the voids. It is important to understand that double- passing through the electroless cop- per increases the likelihood of cohe- sive failure of the copper deposit. Extreme care should be taken to ensure interconnect integrity is not compromised. Regardless, double- passing increases production time and cost. The best defense against small hole voiding is optimizing processes that have a direct effect on the qual- ity of plating in the via. These include drilling, desmear, catalyzation, and the electroless copper process itself. PCB007 Michael Carano brings over 40 years of electronics industry experience with special expertise in manufacturing, performance chemicals, metals, semiconductors, medical devices, and advanced packaging. To read past columns, click here. T RO U B L E I N YO U R TA N K F i g u re 2 : N o vo i d s w i t h a n o pt i m i ze d e l e ct ro l e s s c o p p e r p ro c e s s — s i n g l e p a s s . ▼