Issue link: https://iconnect007.uberflip.com/i/1539283
10 DESIGN007 MAGAZINE I SEPTEMBER 2025 fundamental (clock) frequency is. Because of this increased frequency content in the square waves, we now have frequencies in the RF range present in the standard digital square waves. So, not only should we consider all digital signals as requiring signal integrity considerations and design rules regardless of frequency, but now we also need to consider our digital signals as RF features as well with all the design challenges. You joke about "the bounces," VCC and ground bounce, and designers' struggle to control or eliminate them. What do designers need to understand to defeat the bounces? The bounces are typically associated with parasitic inductance in the design. This includes the inductance of the leads of the device such as the power lead and ground/return lead, the inductance of the transmission lines (traces), and inductance of the vias, as well as any other conduc- tive features in the power distribu- tion network (PDN). This is also associated with the parasitic parameters of the decoupling caps used in the PDN. During a switching event (transition from 0–1 or from 1–0) (also called the rise/fall time of the digital signal) there is no way in the real world to completely eliminate the bounces due to the existence of the parasitic elements of real devices used in PCBs and PBAs. But there are a few techniques that designers can use to minimize these effects. The designer and/or electrical engineer will need to model and simulate the PDN to include all the parasitic elements of the devices rather than the ideal models. For example, every physical capacitor placed on the PBA comes with a "free" resistor and inductor. These are the parasitic elements of the capacitor. Additionally, the designer can look into using alternate component packages that reduce these parasitic properties to minimize the magnitude of the bounces. The designer can consider using a BGA or CSP in place of a QFP (gull-wing) device, as the thin leads and wire frame inside a QFP have significantly higher inductance to the silicon contact pads, rather than the parallel and more direct connections to the silicon contact pads as used in BGA and CSP packages. Finally, the designer or engineer can use additional electrical engineering analysis and circuit modifica- tion to help mitigate these effects further. These include proper signal integrity analysis and design; the use of termination resistors; the addition of flyback diodes to MOSFETs; and other switching devices to reduce the amount of inductive kick/ spike caused by the switching event; and proper selection of decoupling caps. Parasitic inductance and capacitance problems can give rise to "bad actors" like jitter and crosstalk. How can designers stop these before they start? Designers need to consider two main areas of parasitic parameters: the components and the design of the PCB. The selection of the component package can have a significant impact on the parasitic parameters of the device. Traditional IC packaging consists of routing all the connections to the outer perimeter of the silicon die. This is placed in a lead frame and this frame, as the name implies, also contains the device leads, and is then molded into the package form. To make the connection from the silicon die to the lead frame, a small diameter wire, Al, Cu, or Au is used. This small-diameter wire and wire frame shape and material will be seen as added induc- tance to the PDN. The selection of packages that remove or reduce these inductances, such as CSP or BGA that make a direct connection from the silicon die to the transmission line structures, will help greatly reduce the amount of "bad actors" seen in the system. For the PCB itself, there are two areas of concern: the selection of material to improve signal integrity performance and the proper design of the signal integrity structures in the PCB, including transmis- sion lines and planar capacitance. For the design of the PCB signal integrity structures, the proper Kris Moyer