SEPTEMBER 2025 I DESIGN007 MAGAZINE 19
Mitigation tactics against latency:
• Material mastery: Deploy low-Dk laminates
to accelerate signal velocity and weaken his
dielectric grip.
• Trace discipline: Match trace delays with
ruthless accuracy, especially in differential
pairs and timing-critical buses, to sever his
serpentine influence.
• Geometry control: Select transmission line
formats (stripline, CPW) with strategic intent,
balancing shielding and delay to neutralize
his geometric traps.
• Route symmetry: Deploy critical synchronous
buses (like DDR) across perfectly mirrored lay-
ers. This symmetrical routing forms an impen-
etrable barrier, ensuring impedance uniformity
and denying him the imbalance he feeds on.
• Predictive modeling: Use field solvers and
simulation tools to expose hidden delay paths
and preempt his interference before layout
lockdown.
Key Points
• It's often possible to track down the source
after the fact; however, a proactive approach
offers the greatest defense.
• With vigilant stackup planning, disciplined fab-
rication, precise impedance modeling by field
solvers, and well-placed terminations, you can
corner the Terminator before he can strike.
• Switching signals that pass through the cavity
induce noise into other signals. Treating the
plane pair as a radial transmission line and
terminating it in its characteristic impedance
can suppress reflections and standing waves.
• A region under a large BGA densely populated
with vias also appears as a discontinuity
because of the large array of anti-pads eating
a hole in the plane. To open up planes under
BGAs, use via-in-pad, shrink the antipad diam-
eter, and use teardrops to offset antipads.
• Dangling via stubs can distort signals passing
through an interconnect and also decrease
the usable bandwidth of the signal. Back-drill
the plating to remove the residual stub, or
route the signal through the full length of the
via barrel.
• Spacing is the best defense against crosstalk.
Increase the separation between critical traces.
Alternatively, tightly couple the signal to the
reference plane.
• Maintain consistent reference planes beneath
critical signals; avoid splits or gaps. Tie unused
zones to ground or eliminate them.
• Add ground vias near every plane transition
or add decaps to each power plane near the
transition. Create a clear path for return cur-
rents to flow smoothly.
• Match trace delays with ruthless accuracy,
especially in differential pairs and timing-
critical buses.
• Deploy critical synchronous buses (like DDR)
across perfectly mirrored layers. DESIGN007
Resources
1. "Beyond Design: Standing Waves in Multi-
layer PCB Plane Cavities", by Barry Olney.
2. "Beyond Design: How to Handle the
Dreaded Danglers Part 1", by Barry Olney.
3. "Beyond Design: How to Handle the
Dreaded Danglers Part 2", by Barry Olney.
4. "Beyond Design: Dampening Plane Reso-
nance with Termination", by Barry Olney.
Barry Olney is managing director
of In-Circuit Design Pty Ltd (iCD),
Australia, a PCB design service
bureau that specializes in board-
level simulation. The company
developed the iCD Design Integrity
software, incorporating the iCD Stackup, PDN, and
CPW Planner. You can download the software at
www.icd.com.au. To read past columns, click here.
B E YO N D D ES I G N
