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OCTOBER 2025 I DESIGN007 MAGAZINE 23 through-holes, so the probes for the two-port shunt-through test- ing must be placed on the pads on the same side of the board. Having wafer probes next to each other creates extra inductive loop coupling between the exposed probe tips, which may mask out the low DUT impedance we need to measure. Adding to the chal- lenge, this probe tip coupling cannot be calibrated out with the available vector network analyzer (VNA) calibration methods. Adding to the list of challenges, the component density of our sys- tems and subsystems puts poten- tial noise sources and noise vic- tims closer together, giving rise to increased in-system interfer- ence. Figure 3 shows a very com- pact multi-kilowatt power converter. To reduce dis- tribution loss, we need to place the power convert- ers close to the chips, where high-speed signals are concentrated, further increasing the chances for in- system interference. As if this were not enough, there are additional challenges. The nonlinear functions of digital power converters make the PDN validation more com- plex, and the easy conversion between time and frequency domain is valid only in the range of lin- ear operation. As a result, the functionality under very large current transients has to be validated by a custom fixture capable of creating large current transients. The coming years will show what solutions the industry will settle on to solve these challenges. One emerging possibility is using vertical PDN, feeding the high-current supply rails of chips from below the main board rather than relying on hor- izontal power planes in PCBs. In either horizon- tal or vertical PDN, validation of microohm imped- ance remains very difficult. To enable and encour- age cooperation among users, CAD systems, and instrumentation companies, a new open-source PDN challenge has been suggested 5 . The entire CAD package has been made available for down- load 6 . DESIGN007 References 1. "Power Distribution System Design Method- ology and Capacitor Selection," by L. Smith, et al, IEEE Trans. Adv. Package, Vol. 22, No 3, August 1999. 2. "Why 2-Port Low-Impedance Measurements Still Matter," by Istvan Novak, Signal Integrity Journal, January 2020. 3. "3D Connection Artifacts in Modern PDN Measurements," CadenceLive Boston, Sept. 12, 2023. 4. "The Future of Power Integrity through the Eyes of Experience," a presentation by Istvan Novak, DesignCon 2023. 5. "Introducing an Upcoming IEEE Packaging Benchmark," by Istvan Novak, Signal Integrity Journal, April 3, 2024. 6. "New Open Source PCB Design for IEEE EPS TC-EDMS Packaging Benchmark," Samtec. Istvan Novak is the principal signal and power integrity engineer at Samtec, with over 30 years of experience in high-speed digital, RF, and analog circuit and system design and an I-Connect007 columnist. To read past columns, click here. F i g u re 3 : H i g h - p owe r b u s c o nve r te r i l l u st rat i o n 4 . ▼