Issue link: https://iconnect007.uberflip.com/i/1540184
OCTOBER 2025 I DESIGN007 MAGAZINE 33 Z-Target F i g u re 2 : P D N i m p e d a n c e p l ot of P C B ( b l u e) a n d P C B w i t h P KG (g re e n ) . ▼ resent the VRM's behavior across the frequency range of interest. Second, decoupling capacitors must be charac- terized. In this case, the V CCINT supply net initially used 172 Murata decoupling capacitors. Each capac- itor was modeled using resistor-inductor-capaci- tor (RLC) parameters derived from the manufactur- er's specifications, accounting for parasitic effects that influence high-frequency behavior. Many mod- ern PDN tools also support SPICE and S-parameter models for capacitors. Once models are assigned, an IC pin group probe created in between power and GND pins enables the observance of the impedance at the device pins and ensures that the Z-Target require- ment is satisfied. In the produced impedance profile plot (Figure 2), the red horizontal line is the calculated Z-Tar- get requirement of 0.637 mOhm, and the blue plot shows the PDN impedance profile of the PCB and decoupling capacitors. Note the distinct frequency- dependent behavior: VRM and bulk capacitors dom- inate below 1 MHz; local decoupling capacitors are most effective from 1–15 MHz. The current design meets the target impedance up to 12 MHz with only one minor violation at 5 MHz. The resonance peak near 1 GHz is due to power/ground plane capaci- tance interaction. The green plot shows the PCB PDN, but now with the addition of the AMD package model attached. With the addition of the package model (PKG), the PDN is now meeting the target impedance up to 19 MHz. AMD recommends that the board designer modify the board layout and PCB capacitor con- figuration to ensure the PDN impedance meets the target impedance of the 15–20 MHz range. For frequencies beyond 15–20 MHz, the on-package decoupling of the Versal device package will work to ensure that the voltages at the die level remain in the proper operating range. Optimization Strategies After establishing the baseline PDN performance, the designer can explore optimization opportuni- ties. While the initial design follows the AMD soft- ware's recommendations for the Versal adaptive SoC configuration, there may be room for improve- ment in both performance and cost efficiency.