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22 DESIGN007 MAGAZINE I NOVEMBER 2025 the number of power supplies required is increas- ing dramatically with IC complexity, and account- ing for them all has become a real challenge. The high number of supplies leads to higher-layer-count substrates. While in the past, we had more signal routing layers than planes, the opposite is now the case, as the majority of stackup layers are reserved for power distribution. Although this increases cost, it may be a godsend because it segregates criti- cal signals to avoid crosstalk and reduces radiation because of the close coupling of signal traces to the reference planes. Power planes may be segmented into distinct voltage domains to support various supply rails (as illustrated in Figure 2). However, because digital cir- cuits typically share a common ground reference, there is generally no justification for splitting the ground plane. Instead, routing boundaries or keep- out zones should be used to isolate signal paths and prevent cross-domain interference. Splitting the ground plane introduces impedance disconti- nuities, increases crosstalk, and exacerbates EMI and should therefore be avoided. Effective mixed- signal design relies on disciplined routing practices. Ground planes should remain continuous but may be logically partitioned, with carefully placed pass- through gaps in the signal layer keep-out regions to allow control signals to enter and exit sensitive zones without compromising signal integrity. Designing AI-driven GPU systems is an entirely different challenge. Each H100 GPU can consume between 700 and 1,000 watts, necessitating multi- plane stackups with heavy, wide power planes and densely packed via arrays. Operating at a core volt- age of 0.85V, the power distribution network must maintain micro-ohm-level impedance to ensure sta- ble performance. The PCB layout must accommo- date VDD (0.85V), VHBM (1.2V), VDDQ (1.1V), VDDIO (1.8V), and auxiliary power rails (1.8V and 3.3V), each paired with closely coupled ground references for optimal power integrity. These lower core voltages contribute to reduced power consumption and ther- mal output. However, even minor voltage drops can cause instability. Signal integrity constraints are equally demand- ing. Routing for PCIe Gen5 and NVLink (GPU-to- GPU interconnect technol- ogy) requires controlled impedance—typically 85Ω differential—along with precise delay matching and isolation from noisy power domains. These high- speed differential pairs must be tuned carefully using stripline or microstrip geometries adjacent to tightly coupled reference planes. To minimize stubs and reflections, designers should employ back-drilled vias, via-in-pad structures, and blind or buried vias throughout the layout. The multiplane HDI stackup—16 to 20 layers— typically incorporates fifth- order HDI structures (five sequential layers of micro- via technology), embedded B E YO N D D ES I G N Figure 2: Supplies poured under an IC on multiple layers separated by ground planes. ▼