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NOVEMBER 2025 I DESIGN007 MAGAZINE 15 mV at the current sink and 8.5 mV at the PCB edges. Table 1 shows the results for all experiments, with the highlighted rows showing the best cases for each category of experiments. The top-most high- lighted row (board area = 16 in²) is chosen despite the noise voltage being slightly higher than the case above it (board area = 64 in²). This is done because the additional board area does not dras- tically improve the noise voltage (32.1 mV), so the case of 16 in² is simply a more practical case from a space and cost perspective. Important Points to Remember • The dynamic characteristics of the current sink or load determine the effective area in which the capacitance of the PCB can be utilized. • When the PCB is much larger than the calcu- lated effective area, high dielectric materials have minimal impact on noise voltage sup- pression. Better performance is achieved by increasing capacitance, either by minimizing power plane spacing or by increasing the num- ber of plane pairs attached to the current sink. • When the PCB is larger than the calculated effective area, further increases in plane area outside of the effective decoupling radius and area also have minimal impact on performance. • When the PCB is smaller than the calculated effective area, increasing the capacitance by using higher dielectric constant materials can improve noise voltage performance. However, decreasing the spacing or adding additional plane pairs achieves similar, if not better, results. • The PCB is only one part of a PDN. The VRM, discrete decoupling capacitors, chip pack- age, and on-die capacitance are critical in achieving the desired performance. For more on this topic, please read my white paper, Effective Decoupling Radius 4 . DESIGN007 References 1. Right the First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 2, by Lee W. Ritchey and John Zasio. 2. Signal Integrity: Simplified, by Eric Bogatin. 3. Electromagnetic Compatibility Engineering, by Henry W. Ott. 4. "Effective Decoupling Radius," by Kirk Fabbri. Kirk Fabbri is a HyperLynx technical marketing engineering manager for Siemens DISW EBS. P C B A re a L a rg e r t h a n t h e Ef fe ct i ve D e c o u p l i n g A re a Board Area Number of Power Plane Cavities Effective Decoupling Area Dielectric Constant Dielectric Spacing Effective Plane Capacitance Noise Voltage at Load Pin 1 6 i n 2 1 6.6 i n 2 4. 3 3 m i l s 2 .1 3 n F 91 .4 m V 6 4 i n 2 1 6.6 i n 2 4. 3 3 m i l s 2 .1 3 n F 87.1 m V 1 6 i n 2 1 1 .41 i n 2 2 0 3 m i l s 2 .1 3 n F 72 . 3 m V 6 4 i n 2 1 6.6 i n 2 4. 3 1 m i l 6. 3 9 n F 32 .1 m V 1 6 i n 2 1 6.6 i n 2 4. 3 1 m i l 6. 3 9 n F 32 . 8 m V P C B A re a S i m i l a r to t h e Ef fe ct i ve D e c o u p l i n g A re a 6.6 i n 2 2 6.6 i n 2 4. 3 3 m i l s *4. 2 6 n F 3 9.1 m V 6.6 i n 2 2 6.6 i n 2 4. 3 1 m i l * 1 2 .7 7 n F 15.4 mV P C B A re a S m a l l e r t h a n t h e Ef fe ct i ve D e c o u p l i n g A re a 2 i n 2 1 6.6 i n 2 4. 3 3 m i l s 6 4 5 p F 1 2 9.4 m V 2 i n 2 1 2 i n 2 1 4 3 m i l s 2 .1 0 n F 9 3 . 2 m V 2 i n 2 1 2 i n 2 1 4 1 m i l 6. 3 0 n F 33.5 mV 2 i n 2 2 2 i n 2 1 4 3 m i l s *4. 2 0 n F 39.3 mV 2 i n 2 2 2 i n 2 1 4 1 m i l * 1 2 .6 n F 15.5 mV Ta b l e 1 : Re s u l t s of a l l ex p e r i m e nt s w i t h t h e b e st s o l u t i o n s i n re g a rd to n o i s e vo l t a g e s h ow n i n l i g ht g re e n . (*Effective plane capacitance is calculated as twice the value of one power plane cavity since two cavities were formed to see their effects. In reality, it will be slightly less effective since there exists additional via inductance to stitch cavities together.)