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38 I-CONNECT007 MAGAZINE I JANUARY 2026 such as on a lab bench or for worst-case operating conditions. A previous design is not necessary; it sim- ply minimizes iterations and provides the designer with a lot more useful information. Many electrical designs are the next generation of a previous design. Using that previous design, the amount of copper on all layers throughout the board can be characterized. TSDCs can take into account all the previous designs that are desired, mounting conditions, components, environmental conditions, and anything else that impacts the thermal design. Comparing a TSDC to an IPC-2152 Trace Sizing Chart When sizing an electrical trace, the difficulty is, "What is an acceptable trace width for a given thick- ness and applied current when you don't know what the real temperature rise will be?" One solution is to use thermal modeling tools to characterize the minimum and maximum amount of copper through- out a PCB. This is achieved by calculating the effec- tive thermal properties across regions of the board and bounding the problem using the minimum and maximum effective thermal properties characteris- tic of the specific PCB or family of PCBs. Using the effective thermal properties, the amount of power in a defined area can be quantified for a specific tem- perature rise. Bookkeeping the power per square inch for a specific temperature rise will guide the designer toward a more realistic temperature rise for parallel conductors through a stackup. Case Study Standard IPC-2152 current-carrying capacity charts are conservative, based primarily on isolated traces, leaving substantial thermal performance untapped in modern multilayer PCBs. Consider a novel process that quantifies total copper con- tent—including traces, planes, and vias—across all layers of a specific PCB design. By analyzing board areas with minimum and maximum copper con- tent, you can generate technology-specific design charts and compare them directly to IPC-2152. These charts provide designers with critical early insights, enabling safe use of significantly higher current densities, narrower traces, and more com- pact layouts while preserving thermal reliability. Case study: An 8-layer FR-4 board (6" × 8" × 0.071") • Minimum K eff : +88% current capacity over IPC-2152 • Maximum K eff : +187% current capacity over IPC-2152 The Current Problem: Why IPC-2152 Falls Short PCB designers rely on IPC-2221 and IPC-2152 charts to size traces, vias, neck-downs, and flex circuits. The IPC-2152 standard is based on a bare polyimide test board suspended in still air (test method IPC-TM-650 2.5.4.1a), with no copper planes and no real-world boundary conditions. IPC-2221 and IPC-2152 are the basis of almost all online calculators for sizing traces in PCB design. IPC-2152 only improved our understanding of trace temperature rise in individual dielectric materials, poly- imide, and two FR-4 materials. Only the polyimide results were published. All other design guide parame- ters remained from IPC-2221, which dates back to work from the National Bureau of Standards in the mid-1950s. Volunteers from the electronics industry performed all the work that went into IPC-2152. Like other IPC standards, it had no dedicated funding, so further improvements have depended on active industry par- ticipation. Anyone is welcome to join or lead these efforts to advance the standards. Standardization ben- efits us all, and ongoing progress comes from those who choose to contribute. Figure 1 shows the classic IPC-2152 conductor sizing chart. Figure 1: IPC-2152 chart assumes a trace in pure dielectric with no copper planes. Real boards include copper layers, components, and mounting, making IPC predictions undefinably conservative.