IPC International Community magazine an association member publication
Issue link: https://iconnect007.uberflip.com/i/1542698
76 I-CONNECT007 MAGAZINE I JANUARY 2026 What are some of the biggest challenges fac- ing PCB designers and design engineers when designing planes? When designing planes, one challenge involves using traditional copper thickness boards, typically 1-ounce copper, in conjunction with finer pitch SMT packages, such as sub-1 mm BGAs. In these cases, the amount of copper clearance/back-off needed between the plane and the vias that are not con- nected to the plane often causes excessively small/thin copper webs between the pads. This anti-pad leads to an insufficient mirror plane for proper controlled impedance of the digital signals needing to route out from the BGA, and to imped- ance discontinuity and signal integrity problems. If we design with thinner copper for planes to miti- gate this issue, we must pay closer attention to the stackup to ensure proper Z-axis copper balancing. This is necessary to reduce warpage (bow and twist) of the PCB during fab and assembly. Additionally, we need to pay attention to the copper weights of the individual cores. For example, if we try to reduce the weight of the planes only, but the stackup is such that the plane is one side of a core and the other side is a signal layer, we can run into further manufacturing prob- lems due to unbalanced copper weight on cores, even though the overall stackup may be balanced. Along the same lines, there is another problem with clearance in planes with high-density pack- ages, such as BGA, CGA, LGA, PGA, and other BTC packages. The thin webs in the plane under these high-density parts indicate a current density hotspot beneath the part, resulting in a thermal hotspot and an increase in heating/reduction in cooling of the part. Note: These assume that full through-vias are being used under the part. To compensate, we can use microvias or blind/buried vias to transition only those layers that require a connection. However, blind/buried and microvias now require sequential lamination instead of traditional single lamination cycle fabrication. Sequential lamination requires the selection of laminate materials that are suitable for multi- ple lamination cycles, which can cause a change in the dielectric constant of the previously lami- nated layers. This change must be considered when designing the planar capacitance using the laminate material. Lastly, whether using through-vias or blind/buried/ microvias, as we increase the number of layers in our design, the connection of these vias to multi- ple planes simultaneously can cause excessive ther- mal conduction to those pins. Typically, these are the Vcc and GND connections. This excessive ther- mal conduction, while very beneficial during opera- tion, can lead to improper/cold solder joint formation during assembly. We're seeing a proliferation of HDI and UHDI boards. How do these technologies impact plane design? HDI and UHDI virtually necessitate the need for microvia/sequential lamination designs. As previ- ously mentioned, sequential lamination can lead to changes in material properties that impact the design of the planes. The even smaller/finer pitch of the devices used in HDI and UHDI requires the use of even thinner copper, such as sub-half- ounce. The thinner copper used for HDI and UHDI supports the smaller feature geometries (trace and