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40 I-CONNECT007 MAGAZINE I JULY 2026 ELIC Design and Fabrication: Frequently Asked Questions Why choose ELIC over traditional HDI or stacked microvia HDI? ELIC eliminates mechanical through-holes as the primary vertical interconnect, making every layer available for rout- ing. This enables higher density than stacked or stag- gered HDI, supports sub- 100-micron pitch BGA escapes, and reduces layer count, but at the cost of significantly more sequential lamination cycles and tighter process controls. How dense can an ELIC board feasibly be in production? A well-executed ELIC stackup can support line and space geometries down to 25 µm with HDI processes, and sub-25 µm with semi-addi- tive processes such as SAP. Designs that would require 20+ layers in conventional multilayer can often be executed in 12–14 layers. Prac- tical density limits are set by fabricator process capability and yield economics, not by theoretical geometry. What is the biggest single challenge in ELIC fabrication? Registration across the full sequential stack is the most systemic challenge. Because ELIC is built from the center outward—one layer added to the top and one to the bottom with each cycle—the outermost layers carry the greatest accu- mulated positional uncertainty. A shift of ±10–15 µm that is incon- sequential in standard HDI can materially reduce microvia land- ing margin in a six-cycle ELIC build. Via fill quality at each level is equally critical: incomplete fill (a known failure mode docu- mented in IPC-WP-023) creates voids that standard AOI may not detect and that can cause field failures after assembly. What are the most common design mistakes when moving to ELIC? The most common mistakes are: 1) designing at minimum process capability everywhere rather than preserving margin in non-critical areas; 2) apply- ing HDI via stacking rules with- out adjusting for the aspect ratio and fill requirements of deeper stacks; 3) treat- ing solder mask as a finishing detail rather than a precision design parameter; 4) terminat- ing multiple via structures on external layers without moving UHDI circuitry internal; and 5) not modeling the thermal impli- cations of eliminating through- holes from the vertical heat dissipation path. ELIC becomes the appropri- ate architecture when designs require four or more sequen- tial build-up cycles and cannot be routed in a 2-4-2 or 3-2-3 HDI configuration. The yield model is multiplicative: at 99% yield per cycle, a six-cycle build starts at ~94% cumulative yield before test and assembly. At 97% per cycle, that drops below 84%. This compounding effect means supplier process maturity, not theoretical capa- bility, determines production viability. When should the fabricator be involved in an ELIC design? As early as possible, ideally before the stackup is final- ized. By the time routing is complete, the structural deci- sions that drive yield and reli- ability are already locked in. Early fabricator engagement prevents the most costly DFM gaps: stackup over-aggression, via aspect ratio mismatches, solder mask strategy errors, external-layer via termination issues, and thermal manage- ment assumptions that do not survive the removal of through- hole copper. Where is the tipping point after which ELIC becomes viable or impractical for production?